How do you create a power switch with create_power_switch, and what are its input/output/ control ports?

Short Answer

create_power_switch (UPF) declares an abstract switch that passes an always-on input supply to a switched output supply under a control signal. You name its ports and the nets they connect to, then write Boolean on and off states in terms of the control port. It is one abstract switch in the UPF, later mapped to library cells and built as an array of many cells.

Technical Explanation

• -input_supply_port {VDDG VDD1p0}: the switch-side port name and the always-on net that feeds it.
• -output_supply_port {VDD VDD1p0_SW}: the switched net; this is what becomes the PD_COP primary.
• -control_port {EN U_PC/PSE}: the control pin and the always-on logic net driving it.
• -on_state {SW_on VDDG {EN}}: state name, which input supply passes, and the expression that turns it on. -off_state gives the off expression.
• -ack_port {ACK U_PC/PSE_ACK}: an acknowledge back to the controller, so U_PC knows the rail is up.
• -domain PD_COP sets the scope where the switch is created. The switch name must be a simple name unless ICC2 is told otherwise.
• The control and ack nets must stay on while PD_COP is off, or you cannot wake the domain.

# [UPF]  mychip.upf
create_power_switch PD_COP_SW -domain PD_COP -input_supply_port {VDDG VDD1p0} -output_supply_port {VDD VDD1p0_SW} -control_port {EN U_PC/PSE} -ack_port {ACK U_PC/PSE_ACK} -on_state {SW_on VDDG {EN}} -off_state {SW_off {!EN}}
map_power_switch PD_COP_SW -domain PD_COP -lib_cells {HEADER_X4}
# [ICC2]  icc2_shell
check_mv_design

What To Check

• The input supply port connects to an always-on net, here VDD1p0.
• The output net is the one bound as the PD_COP primary.
• On and off expressions are complementary and match the cell control polarity.
• Control and acknowledge nets come from always-on logic.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): check_mv_design is clean, VDD1p0_SW is the PD_COP primary, and EN traces to U_PC in PD_MYCHIP.
• Suspicious (illustrative): The ack port is left unconnected, so U_PC has to wait a fixed time instead of a real acknowledge.
• Hard stop: PSW_CONTROL_CONN from VC LP, or the output port bound to VDD1p0 so PD_COP never switches.

What The Interviewer Is Testing

• Can you name each port and the net behind it?
• Do you know the on_state expression must match the real control polarity?

Follow-up Question & Model Response

"If PD_COP needs 2,000 switch cells, why does the UPF still show one switch?"

Candidate Model Response: The UPF describes power intent, not cells. PD_COP_SW is an abstract model of one input, one output and one control. map_power_switch picks the library cell, and ICC2 builds the physical array with create_power_switch_array or create_power_switch_ring, then chains control through connect_power_switch. All 2,000 cells implement the one switch in the UPF.