What is the difference between a header switch and a footer switch?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A header switch is a PMOS transistor between the real power rail VDD and the domain's virtual power rail. A footer switch is an NMOS transistor between the domain's virtual ground and the real ground VSS. Both cut the same current path, just from different sides.
Technical Explanation
- A header is PMOS on the VDD side: it connects the power rail to the power pins of the cells in the domain.
- A footer is NMOS on the VSS side: it connects the ground rail to the ground pins of the cells in the domain.
- With a header, the domain sees a switched VVDD and a real VSS; with a footer, a real VDD and a switched VVSS.
- The PMOS header conducts when its gate is low, so driving SLEEP high on its gate turns it off.
- The NMOS footer conducts when its gate is high, so it takes the inverted signal, SLEEP_N, or an active-high enable.
- Most designs gate only one rail. Which one to pick is a design decision covered on the expert page.
- Either way, isolation, retention and always-on cells in the domain must connect to the rail that stays real.
Common Mistake
The Trap: Assuming a shutdown domain gates both VDD and VSS.
- A beginner then draws the wrong supply connections for isolation and retention cells, which need to know which rail stays real.
- Mixing up the control polarity is the other classic slip: the domain powers down when the controller meant to wake it.
Follow-up Question & Model Response
"With a footer switch, what stays connected when the domain is off?"
Candidate Model Response: VDD stays connected to every cell in the domain, and only the ground path is broken. The internal nodes drift up toward VDD instead of down toward 0 V. Isolation cells still see invalid outputs, so they are still needed. Any always-on cell must reach the real VSS rather than VVSS. Retention latches need the real VSS too, alongside their backup power.
Practical Example
Design Scenario: (illustrative) A 0.9 V block with a HEADER_X4 PMOS: VDD at 0.9 V feeds the switch, VVDD feeds the rows, VSS is shared. The same block with a FOOTER_X4 NMOS: VDD feeds the rows directly, VVSS is the rows' ground, and the switch ties VVSS to VSS. In both cases, turning the switch off stops current through the block. HEADER_X4 takes SLEEP directly, so SLEEP high opens it. FOOTER_X4 takes SLEEP_N, produced by an inverter on the always-on supply.
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