IntermediateQuestion 11 of 60

How do you specify save and restore signals with set_retention_control?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

You name each control net and its active level or edge: -save_signal {U_PC/SAVE high} and -restore_signal {U_PC/NRESTORE low}. In IEEE 1801-2015 these options sit on set_retention (UPF) itself; set_retention_control (UPF) is the UPF 1.0 form that ICC2 and PrimeTime still accept. The sense you write must match the retention cell pins, or the flop saves and restores at the wrong moments.

Waveform of a PD_COP power cycle: the PD_COP clock stops, U_PC/SAVE pulses high while VDD1p0_SW is still at 1.0 V, VDD1p0_SW falls to 0 V (hatched off period), ramps back to 1.0 V, then U_PC/NRESTORE pulses low before the clock restarts; each pulse is labelled with its -save_signal or -restore_signal {net sense} (UPF) setting. — Technical Reference DiagramHow do you specify save and restore signals with set_retention_control?

Technical Reference DiagramHow do you specify save and restore signals with set_retention_control?

Technical Explanation

Save: the net and sense that copy the flop into its shadow latch. Assert it with the clock stopped and the primary still on.
Restore: the net and sense that copy the shadow back. Assert it only after the primary rail is stable again.
Sense: high, low, posedge or negedge. An active-low pin such as NRESTORE needs low, not high.
Signal source: a port, pin or net; ICC2 punches ports as needed. The driver must be always-on logic such as U_PC.
Legacy form (still accepted by ICC2/PT): the same -save_signal and -restore_signal on a separate set_retention_control (UPF) line.
ICC2 parses -save_condition and -restore_condition but does not use them; they matter to simulation.
A wrong sense passes synthesis: the flop saves during normal operation or restores stale data.

# [UPF]  mychip.upf
set_retention PD_COP_RET -domain PD_COP -retention_supply SS_AON -elements {U_COP/reg1 U_COP/pc U_COP/int_state} -save_signal {U_PC/SAVE high} -restore_signal {U_PC/NRESTORE low}
# [ICC2]  icc2_shell
report_mv_cells -retention
# [VC LP]  vc_static_shell
check_lp -stage design
report_violations -app LP

What To Check

Each sense matches the active level of the mapped cell pin.
SAVE and NRESTORE come from always-on logic and never assert together.
SAVE fires before the switch opens; NRESTORE fires after the rail settles.
Legacy files have exactly one control line per retention strategy.

Command Checks & Actions

UPF (design.upf)

set_retention PD_COP_RET -domain PD_COP -retention_supply SS_AON -save_signal {U_PC/SAVE high} -restore_signal {U_PC/NRESTORE low}

Attach save and restore nets and senses to the strategy

ICC2 (icc2_shell)report_mv_cells -retention

Confirm which retention cells implement the strategy

VC LP (vc_static_shell)check_lp -stage design

Statically check retention control against the power intent

VC LP (vc_static_shell)report_violations -app LP

List the low-power violations found

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): The strategy shows SAVE high and NRESTORE low, matching the RET_DFF_X1 pins, and VC LP reports no retention violations.
Suspicious (illustrative): SAVE and NRESTORE come from different clock domains in U_PC with no handshake between them.
Hard stop: A save or restore net driven from PD_COP itself, or a sense opposite to the cell pin.

Common Mistake

The Trap: Writing -restore_signal {U_PC/NRESTORE high} for a cell whose restore pin is active-low.

The flop restores continuously in normal operation, overwriting live state with the shadow copy, and only simulation or silicon shows it.

What The Interviewer Is Testing

Do you know where the signals live in 1801-2015 versus UPF 1.0?
Can you place save and restore correctly around the rail ramp?

Follow-up Question & Model Response

"Why must restore wait until after the rail is stable?"

Candidate Model Response: The main flop only captures reliably once its own supply is back in range. If NRESTORE asserts while VDD1p0_SW is still ramping, the transfer can land partly or not at all. U_PC usually waits for the switch acknowledge, which returns only after the switch chain is on. Then it restores, releases isolation and restarts the clock.

Practical Example

Design Scenario: (illustrative; RET_DFF_X1 is an illustrative cell name with pins SAVE and NRESTORE) PD_COP_RET maps to RET_DFF_X1. U_PC stops the PD_COP clock, pulses SAVE high for 2 cycles, then turns the switch off. On wake, U_PC waits for PSE_ACK with VDD1p0_SW back at 1.0 V, drives NRESTORE low for 2 cycles, releases isolation and restarts the clock. The UPF says exactly this: SAVE high and NRESTORE low.

Low-Power & UPF Handbook