What is a retention signal (save/restore), and why is it needed?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Retention signals are the control inputs, usually SAVE and RESTORE, that tell retention registers when to copy their state into a backup latch and when to copy it back. The always-on power controller drives them around each power-down and wake-up. Without them the domain loses its state and must fully reset and reinitialise on every wake-up, which costs time, energy and a software setup pass.
Technical Explanation
- SAVE tells each retention register to copy its value into the backup latch before the switch opens.
- RESTORE tells it to copy the saved value back after power returns and the rail settles.
- The power controller in an always-on domain issues both, in order with isolation and the switch enable.
- The nets cross the switchable area to reach every retention flop, so any buffering on them must use always-on cells with a backup supply.
- In IEEE 1801-2015 you name them on
set_retention(UPF):-save_signal {save high}and-restore_signal {restore high}. - Legacy form (still accepted by ICC2/PT):
set_retention_control(UPF), which carries the same save and restore signals. - If level-sensitive SAVE and RESTORE are asserted together, IEEE 1801 simulation corrupts the register by default.
Common Mistake
The Trap: Routing SAVE and RESTORE through ordinary buffers inside the switchable domain, because they look like any other control net.
- The signals die with the rail, so restore never happens and the domain wakes up with lost state.
- Power-aware simulation shows it as X on the retained flops after wake-up, but only if the test really powers the domain down.
Follow-up Question & Model Response
"Why not just reset the domain on wake-up instead of using retention?"
Candidate Model Response: A reset is fine when the state is cheap to rebuild. For a CPU or a large configuration block, reinitialising takes many cycles and energy, and software has to redo the setup. Retention keeps only the flops that matter and brings them back in a few cycles. The cost is larger flops and always-on control nets. Many designs mix both: retain the control state and reset the datapath.
Practical Example
Design Scenario: (illustrative) In MYCHIP, U_PC drives save and restore nets to the 256 retention flops of PD_COP. Before shutdown it stops the PD_COP clock, asserts ISE, pulses save, then drops PSE. On wake-up it raises PSE, waits for PSE_ACK, then pulses restore. Only after that does it release ISE and restart the PD_COP clock. Both control nets cross PD_COP through always-on buffers powered from VDD1p0.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising