What is output load, and why does it affect delay?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
Output load is the total capacitance a cell's output pin must charge or discharge — the sum of all downstream receiver input pin capacitances plus routed wire capacitance. Higher capacitive load requires more time to charge (I = C·dV/dt), directly increasing propagation delay and slowing output slew.
Mentor explanation
Output load dictates the RC charging time constant of the driving gate.
Key terms
- Pin capacitance (C_pin) — the characterized input capacitance of every fanout receiver pin on the net.
- Wire capacitance (C_wire) — parasitic capacitance between routed metal wires, ground planes, and adjacent layers.
- Fanout — the number of receivers a driver feeds; high fanout multiplies pin capacitance directly.
- Drive strength / upsizing — the standard fix for load-induced delay: swap in a cell with wider transistors (e.g., BUF_X1 → BUF_X4) to source more charging current.
On high-fanout nets (resets, enables, clocks), receiver pin capacitance often dominates the total load rather than wire capacitance. Always check receiver fanout count before assuming wire length is the root cause of high load.
Practical example
Total Load Calculation Example:
Net 'data_bus_0':
Driver: U1/Y (INV_X2, I_drive = 0.8mA)
Fanouts: 4 x DFF_X1 (C_pin = 1.2 fF each -> Total C_pin = 4.8 fF)
Wire: 250um M3 metal route (C_wire = 18.5 fF)
---------------------------------------------------------
Total Output Load C_load = 4.8 fF + 18.5 fF = 23.3 fFInterview trap
Assuming output load is mostly wire capacitance. On high-fanout nets, pin capacitance from receivers frequently outweighs wire capacitance.
Key takeaways
- Output load = Sum of all fanout Pin Capacitances + Interconnect Wire Capacitance.
- Propagation delay is directly proportional to load capacitance: t_delay ∝ (C_load / I_drive).
- High output load also degrades output slew, compounding delay into the next logic stage.
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- Say how you would verify it in a real flow.
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