What is input slew, and why does it change a cell's delay?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
Input slew is the transition time required for an input voltage edge to ramp between logic thresholds (e.g. 10%–90% or 20%–80%). Slower input slew keeps internal transistors in their high-resistance transition region longer, delaying switching and degrading output transition time.
Mentor explanation
Input slew directly dictates how quickly internal transistors transition from cutoff to saturation.
Key terms
- Slew / transition time — the rise or fall time of a signal, the primary "edge rate" metric in STA alongside delay itself.
- Short-circuit (crowbar) current — during a slow transition, both pull-up and pull-down networks remain partially active simultaneously, wasting power and slowing the output.
- Slew propagation / cascade effect — a degraded output slew on one gate becomes the degraded input slew for the next gate down the datapath.
set_max_transition— the design rule constraint that caps maximum transition time, preventing delay math from extrapolating outside characterized Liberty ranges.
Slew problems propagate: a single badly-driven high-fanout net can inflate delay across its entire downstream logic cone, which is why max-transition design rules are fixed before trusting path slack numbers.
Practical example
Slew Measurement Thresholds:
Voltage
Vdd ─────────────────────────────── 100%
............................... 90% / 80% (Upper Slew Threshold)
- - - - - - - - - - - - - - - - 50% (Delay Reference Point)
............................... 10% / 20% (Lower Slew Threshold)
GND ─────────────────────────────── 0%
|<-- Slew Time -->|Interview trap
Thinking slew only affects the single gate it arrives at. It cascades — a degraded input slew produces a degraded output slew, penalizing the entire downstream fanout cone.
Key takeaways
- Input slew is the 10%-90% or 20%-80% transition time of the driving voltage waveform.
- Degraded (slow) input slew directly increases cell delay and internal short-circuit power.
- Timing closure requires resolving max-transition DRC violations before trusting path slack.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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