Why doesn't a standard cell have just one fixed delay?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
A standard cell does not have a single fixed delay because delay depends dynamically on the specific electrical operating conditions it experiences: its PVT corner, its input transition time (input slew), and the capacitive load on its output pin (C_load).
Mentor explanation
Standard cell delay is an interpolated dynamic function of input slew and output capacitive load.
Key terms
- Input slew (transition time) — how fast the input voltage ramps; a slower ramp keeps transistors in their resistive region longer, adding delay.
- Output load (C_load) — everything the output has to charge/discharge: downstream receiver pin capacitances plus wire capacitance.
- Timing arc — the specific input-to-output path being timed (which input pin, rising or falling); different arcs on the same cell have different delays.
- NLDM/CCS lookup table — the 2D (or richer) table in the Liberty file, indexed by (input slew, output load), that the STA engine interpolates to compute the instance delay.
The same buffer placed in two different spots of the same design will report two different delays — one driving a short local net with light load, the other a long global net with heavy load and worse input slew. That is the delay model correctly reflecting each instance's real electrical environment.
Practical example
Delay Function Representation:
Delay_cell = f(PVT Corner, Input Slew t_{in}, Output Load C_{load}, Arc A → Y, Transition R/F)
Liberty LUT Table Lookup (NLDM):
C_load -> [5fF] [20fF] [50fF]
Slew: 10ps | 18.2ps 24.5ps 38.1ps
Slew: 40ps | 28.7ps 35.9ps 51.2ps
Slew: 120ps | 46.1ps 56.8ps 74.9psInterview trap
Treating a datasheet delay as if it were a single fixed number for the cell. Delay is always computed per-instance from a multi-dimensional table lookup, not read off a spec sheet.
Key takeaways
- Cell delay depends on Input Slew, Output Load (C_load), PVT Corner, and Timing Arc.
- Liberty libraries use 2D/3D Look-Up Tables (NLDM/CCS) with bilinear interpolation.
- The exact same buffer will exhibit different delays at different locations in the layout based on routing capacitance.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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