Level 2: Construction & Debugging

Intermediate MMMC Interview Questions

Learn to construct, activate, validate, and debug real MMMC environments across Cadence and Synopsys flows.

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What to practise at this level

Focus on object reuse, activation, coverage, and view-first debugging. Be ready to distinguish universal concepts from vendor-specific commands.

  1. 01 Why can the exact same physical path pass timing in one view and fail in another?Intermediate: A path's physical gates and wires are identical across views, but its operational frequency (mode), cell switching speeds (PVT corner), wire delays (RC corner), and active timing exceptions differ between views, producing different arrival and required times in each view.
  2. 02 Can one constraint mode be reused with multiple delay corners?Intermediate: Yes. Reusing one constraint mode across multiple delay corners is the standard MMMC methodology. It guarantees that functional timing intent (clock frequencies, I/O budgets, exceptions) remains identical across all physical process and environmental corners.
  3. 03 Can one delay corner be reused across several different modes?Intermediate: Yes. A delay corner is purely physical (a specific PVT and RC condition). Physical transistor and wire physics remain identical regardless of whether the chip is running functional data, scan test patterns, or BIST.
  4. 04 Why is "SS means setup, FF means hold" an unsafe rule to lean on?Intermediate: "SS means setup, FF means hold" is unsafe in advanced FinFET nodes because temperature inversion can make cold (-40°C) slower than hot (125°C) for setup, while gate-dominated and wire-dominated paths have different worst RC corners.
  5. 05 What's the difference between creating an analysis view and activating it?Intermediate: Creating an analysis view (`create_analysis_view`) registers the view definition in the database without evaluating timing. Activating it (`set_analysis_view -setup {...} -hold {...}`) instructs the timing engine to build the timing graph, compute slack, and optimize against that view.
  6. 06 A view exists in the database but isn't active for setup or hold. What does that actually mean for signoff?Intermediate: An unactivated view is completely ignored by the timing engine — no slack is calculated, no paths are checked, and no violations are reported. It creates a dangerous silent escape because summary reports show zero violations, mimicking a clean signoff.
  7. 07 Walk through how you'd debug one unexpected timing violation.Intermediate: To debug an unexpected timing violation, start by validating constraint integrity (`check_timing`) to rule out false paths or clock definition errors, then inspect a full-clock expanded timing report (`report_timing -path_type full_clock_expanded -input_pins -nets -capacitance -transition_time`) to isolate whether the root cause is clock skew, high cell delay, or wire RC/crosstalk.
  8. 08 What's the conceptual difference between a Cadence analysis view and a Synopsys scenario?Intermediate: Cadence (Innovus/Tempus) and Synopsys (ICC2/PrimeTime) represent the same concept (mode × corner), but structure it differently: Cadence uses an explicit 4-tier assembly (`library_set` + `rc_corner` → `delay_corner`, paired with `constraint_mode` → `analysis_view`), while Synopsys combines scenario SDC and corner operating conditions directly inside `create_scenario`.
  9. 09 Why can a path become newly critical only after routing, when it looked fine before?Intermediate: Pre-route timing relies on estimated wire lengths (global routing or virtual routes) with ideal slews and zero crosstalk. Detailed routing introduces actual metal layer assignments, via resistance stacks, detour routing around congestion, and signal integrity crosstalk coupling from switching neighbors.
  10. 10 What is scenario or view explosion, and why not just analyze every mathematical mode-times-corner combination during optimization?Intermediate: Scenario explosion occurs when multiplying multiple modes by many physical corners produces hundreds of analysis views (e.g. 10 modes × 15 corners = 150 views), exhausting memory and bloating PnR runtimes. The solution is dominant scenario pruning during PnR, expanding to the full matrix for final signoff.

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