Why is "SS means setup, FF means hold" an unsafe rule to lean on?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
"SS means setup, FF means hold" is unsafe in advanced FinFET nodes because temperature inversion can make cold (-40°C) slower than hot (125°C) for setup, while gate-dominated and wire-dominated paths have different worst RC corners.
Mentor explanation
Modern signoff requires verifying both temperature extremes and interconnect corners.
Key terms
- Temperature inversion — at near-threshold voltages (sub-0.8V), threshold voltage shifts dominate over mobility, making -40°C the slower, setup-critical condition.
- Gate vs wire dominance — capacitance-dominated paths are worst at Cworst; resistance-dominated paths are worst at RCworst.
- Cross-domain clock skew — OCV variation on fast corners can induce setup violations on cross-domain interfaces through clock skew.
Never answer "which corner is setup-critical?" with a single corner code. The correct answer is that setup must be verified at both temperature extremes and across both Cmax and RCmax interconnect corners.
Practical example
Temperature Inversion Delay Comparison (5nm Cell):
Buffer BUF_X1 @ 0.65V Vdd:
• Temp = +125°C: Delay = 42.5 ps
• Temp = -40°C: Delay = 51.8 ps <-- 22% SLOWER AT COLD! (Worst Setup)Interview trap
Answering that Slow-Slow is always the setup-critical corner. In advanced FinFET nodes, temperature inversion makes -40°C setup-critical at low voltages.
Key takeaways
- Temperature inversion causes ultra-low voltage FinFET cells to be slower at -40°C than at +125°C.
- Cworst limits short gate-heavy paths; RCworst limits long wire-heavy paths.
- Signoff requires explicit analysis across both temperature extremes and all interconnect corners.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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