What is a "mode," in plain terms?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
A mode is what the chip is doing at a given moment — functional execution, scan shift, scan capture, memory BIST, or low-power standby — on the exact same physical netlist. Nothing about the silicon changes between modes; only which clocks are toggling, which control pins are pinned to constants, and which timing constraints apply.
Mentor explanation
A mode represents behavioral and constraint intent on identical silicon hardware.
Key terms
- Case analysis [SDC:
set_case_analysis] — forces a control pin to a fixed 0 or 1 for a mode, which prunes the logic STA actually needs to check (a muxed path only exists for the value that selects it). - Functional mode — normal mission-mode operation at target system clock frequency.
- Scan shift / capture mode — test modes where flops are chained into shift registers (shift is hold-critical, capture can be at-speed or slow).
- BIST mode — a built-in-self-test engine exercises memories or logic on its own dedicated clock.
The reason this matters for timing: a path that's perfectly real in functional mode (say, a control register feeding an ALU) might be functionally frozen or irrelevant during scan shift, so it shouldn't even be timed the same way there. Each mode needs its own SDC — its own clocks, case values, and exceptions — because those things are genuinely different per mode, not just relabeled.
Practical example
SDC Mode Separation Example:
# In functional mode SDC:
set_case_analysis 0 [get_ports test_mode_en]
create_clock -period 1.0 -name CORE_CLK [get_ports clk_in]
# In scan shift mode SDC:
set_case_analysis 1 [get_ports test_mode_en]
create_clock -period 20.0 -name SCAN_CLK [get_ports scan_clk_in]Interview trap
Confusing a mode with a power domain or a process corner. A mode is purely behavioral/constraint-driven — it has nothing to do with voltage rails or manufacturing variation, which is what corners describe.
Key takeaways
- A mode is a distinct behavioral operating configuration of the circuit.
- The physical netlist and cell locations do not change between modes — only the active clocks, case constants, and constraints change.
- Each mode requires its own dedicated SDC file or constraint mode object.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
MMMC Signoff Guide
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Explore the full 10-chapter MMMC guide on modes, PVT corners, RC parasitics, analysis views, and correlation between implementation and signoff tools.
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