Why can a path become newly critical only after routing, when it looked fine before?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
Pre-route timing relies on estimated wire lengths (global routing or virtual routes) with ideal slews and zero crosstalk. Detailed routing introduces actual metal layer assignments, via resistance stacks, detour routing around congestion, and signal integrity crosstalk coupling from switching neighbors.
Mentor explanation
Post-route timing captures physical layout parasitics that do not exist during placement.
Key terms
- Global Route (GR) vs Detailed Route (DR) — GR estimates routing topology; DR creates physical metal tracks and vias.
- Via stack resistance — dropping through 5 metal layers adds significant lumped series resistance.
- Layer demotion — congestion forces timing-critical signals onto resistive lower metal layers (M1–M3).
- Crosstalk delta delay (Delta t) — parallel wire adjacency causes capacitive coupling that slows transitions.
Congestion and pin density force nets into tortuous detour routes and lower metal layers, creating post-route timing bottlenecks on previously clean paths.
Practical example
Pre-Route vs Post-Route Path Degradation:
Net 'reg_to_alu_3':
• Pre-Route (Steiner Estimate): Length = 120um, Layer = M4 (avg), Vias = 2 -> Net Delay = 12ps
• Post-Route (Extracted SPEF): Length = 340um (Detour!), Layer = M2, Vias = 8 -> Net Delay = 85ps
• Crosstalk Delta Delay (SI): +35ps pushout due to adjacent bus switching
-------------------------------------------------------------------------------------------
Total Interconnect Delay: 12ps (Pre-Route) -> 120ps (Post-Route) -> 108ps Slack Degradation!Interview trap
Assuming that pre-route timing closure guarantees post-route tapeout success. Unmodeled via resistance, detour routing, and crosstalk coupling frequently create new critical paths after detailed routing.
Key takeaways
- Pre-route timing uses ideal Steiner wire estimates without coupling capacitance.
- Detailed routing introduces actual wire detours, via stack resistances, and layer assignments.
- Post-route SPEF extraction and Signal Integrity (SI) crosstalk delta delay reveal real silicon parasitics.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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