BeginnerQuestion 12 of 20Source page 6

Why isn't a routed wire just an ideal connection?

From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series

Direct answer

A routed wire has distributed resistance and capacitance that scale delay quadratically (t ∝ L²) for unbuffered lines, degrades signal transition times like a low-pass filter, adds via resistance, and exposes signals to crosstalk noise from adjacent switching neighbors.

Technical Reference DiagramWhy isn't a routed wire just an ideal connection?

Mentor explanation

Routed interconnect behaves like a distributed RC transmission line rather than an ideal conductor.

Key terms

  • Distributed RC delay (Elmore delay) — wire delay scales with the square of length (t ∝ L²) for unbuffered lines because R and C are distributed along the entire length.
  • Via resistance — every layer change (e.g. M1 to M6) adds 5–20Ω of resistance in series, creating localized RC bottlenecks.
  • Slew flattening — high wire RC acts as a low-pass filter, converting sharp transitions into slow ramps and increasing receiver delay.
  • Repeater/buffer insertion — breaking long wires into shorter segments with buffers to restore linear (t ∝ L) delay scaling.

Physical design tools insert buffer repeaters at regular intervals on long nets to prevent quadratic delay explosion and maintain fast signal slews.

Practical example

Elmore Delay Comparison:

  • Short local net (50 µm): R = 15Ω, C = 4fF ⟹ t_{net} ≈ 0.06ps (Negligible)
  • Long global net (1500 µm unbuffered): R = 450Ω, C = 120fF ⟹ t_{net} ≈ 27ps (Plus massive cell delay penalty on the driver!)

Interview trap

Computing wire delay as simply R_total × C_total. Distributed Elmore wire delay is 0.5 × R_total × C_total, and without repeaters delay scales quadratically with wire length.

Key takeaways

  • Unbuffered long wire delay grows quadratically with length (t ∝ L^2).
  • Wire RC acts as a low-pass filter, degrading downstream slew rates.
  • Buffer insertion is essential to maintain linear delay scaling on long interconnects.
Self-check: can you answer this aloud?

Try a 45-second answer using this structure:

  1. State the direct answer.
  2. Explain the timing or physical reason.
  3. Name one caveat.
  4. Say how you would verify it in a real flow.

MMMC Signoff Guide

Explore the full 10-chapter MMMC guide on modes, PVT corners, RC parasitics, analysis views, and correlation between implementation and signoff tools.

Offline PDF Bundle

Want all 1109 questions offline?

Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.

See what's inside the bundle
Static Timing Analysis (STA) Handbook — ten chaptersSTA HandbookTen chapters on setup, hold, OCV, and PrimeTime signoff.