What does a gate-level netlist contain?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A gate-level netlist describes your circuit purely as connectivity — instances of library cells or modules, wired together by nets — it captures what connects to what, not where anything physically sits or what shape the wires will eventually be. Think in terms of a simple electrical vocabulary: a cell is a component, a pin is its terminal, a net is a wire connecting terminals, and an instance is one particular usage of a cell (the same inverter cell might be instantiated hundreds of times under hundreds of different instance names).
Technical Explanation
- A gate-level netlist describes your circuit purely as connectivity — instances of library cells or modules, wired together by nets — it captures what connects to what, not where anything physically sits or what shape the wires will eventually be.
- Think in terms of a simple electrical vocabulary: a cell is a component, a pin is its terminal, a net is a wire connecting terminals, and an instance is one particular usage of a cell (the same inverter cell might be instantiated hundreds of times under hundreds of different instance names).
- In Verilog terms:
moduledeclarations describe hierarchy,portdeclarations describe interfaces,wiredeclarations name the connections, and instantiation statements wire specific library cell pins to those named wires. - The netlist you receive for implementation is normally already technology-mapped — meaning generic RTL logic has already been converted into the specific library cells your synthesis tool selected, not abstract gates.
- Depending on the upstream DFT/synthesis flow, this netlist may already contain scan flip-flops, clock-gating cells, tie-off cells, or low-power cells — don't try to guess the insertion stage just from the filename; check the actual synthesis and DFT handoff reports to know for sure.
- Before trusting a netlist, verify the basics: top module name, hierarchy structure, port directions and widths, expected cell counts, and that library models actually exist for every referenced cell.
- Two red flags worth actively hunting for: unintended undriven nets (a pin expecting a driver that has none) and multiple drivers on the same net (a connectivity conflict). A black-boxed macro is only acceptable if its interface and required models are genuinely supplied through your approved flow — an undocumented black box is a landmine, not a shortcut.
Visual Verification
Structural netlists instantiate library masters (such as AND2_X1 and INV_X1) under unique instance names (U10, U12, U45) to define precise gate-level connectivity prior to geometric placement.
Command Checks & Actions
read_verilog design.vLoads the netlist; at this point only instance and connectivity data exists in the design, confirming a gate-level netlist by itself carries no timing or physical information.
link_block -rebindResolves every netlist instance against the loaded libraries. Any instance the netlist references that no library actually provides shows up here, not at read_verilog time.
Common Mistake
The Trap: Candidates often mistakenly treating a net name as a cell name, or assuming that a connected netlist proves timing correctness.
Follow-up Question & Model Response
"Can placement change the netlist?"
Candidate Model Response: Optimization can resize or insert cells and alter connectivity while preserving the required logical behavior; equivalence checking validates that behavior.
Practical Example
Tapeout Scenario: INV_X1 u_inv (.A(data_in), .Y(n1)); names INV_X1 as the cell type, u_inv as the instance, A and Y as library pins, and data_in and n1 as nets. It says nothing about u_inv's final x/y coordinates.
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