Physical Design Inputs, Pre-Floorplan Sanity, and Floorplanning: Interview Guide

1. Direct Answer & PnR Overview

In modern ASIC design flows (using Synopsys IC Compiler II or Cadence Innovus), physical design bridges the architectural RTL intent and foundry fabrication rules. Flaws in early inputs propagate into unfixable routing congestion or timing failures post-route.

2. Core Physical Design Inputs & Collateral Checklist

Before launching physical implementation, physical design engineers validate a comprehensive collateral checklist:

• Gate-Level Netlist (Verilog): Structural netlist produced by synthesis (Design Compiler / Genus). Must be cleanly linked without unresolved black boxes or floating inputs.
• Timing & Power Libraries (.lib / .db): Liberty format files defining pin capacitance, cell delay lookup tables (NLDM / CCS / ECSM), setup/hold margins, leakage power, and dynamic power across all PVT corners.
• Physical Layout Libraries (LEF / NDM / CEL): Standard cell and macro abstract views detailing bounding boxes, pin shapes, metal layer obstruction geometries, and antenna properties.
• Technology File (tf / tech-LEF): Defines physical layer stack rules, dielectric constants, minimum width/spacing rules, preferred routing directions, and via definitions.
• SDC Timing Constraints: Design clock definitions, input/output delays, multicycle paths, false paths, and clock group relationships.
• Power Intent (UPF / CPF): IEEE 1801 power domain definitions, supply nets, isolation rules, level shifter rules, and power switch strategies.
• Parasitic Extraction Models (TLU+ / ITF / QRC Tech): Interconnect RC extraction tables modeling metal resistance and capacitance variations across temperature and process corners.

3. Input Collateral Formats & Verification Matrix

4. Manufacturing Grids, Placement Sites & Pin Access

FinFET sub-7nm design relies on multiple coordinate grids:

If standard cell pins fail to land precisely on legal routing track intersections, the detailed router generates local DRC spacing violations or requires expensive multi-cut jumper vias.

5. Pre-Floorplan Sanity Quality Gates

Never proceed to floorplanning or placement without executing the Pre-Floorplan Sanity Gate. This quality review catches structural flaws that would otherwise waste weeks of runtime:

• Link Integrity: Verify zero unresolved black boxes or unlinked hierarchical modules.
• Constraint Validation: Check for unconstrained I/O ports, missing clock definitions, and unconstrained sequential pins using check_timing.
• High Fanout Nets: Identify resets, scan-enables, and global control nets that must be treated as ideal during early placement.

6. Die Sizing, Core Utilization & Aspect Ratio

The floorplan determines the physical boundaries, macro placement, power grid network, and I/O pad ring of the integrated circuit:

A typical initial target utilization ranges between 65% to 75% to reserve whitespace for CTS buffer insertion, hold buffer ECOs, routing detours, and power dissipation decaps.

7. Macro Placement, Halos & Channel Blockages

Hard macros (SRAMs, ROMs, analog PHYs) must be positioned around the core periphery, keeping the center open for standard cell logic paths. Macro placement rules include:

• Keep macro pins facing toward the core standard cell area to minimize interconnect wire length.
• Maintain uniform macro orientation to ensure power strap and well connections align cleanly.
• Define Keepout Halos around macros to prevent standard cells from placing too close to macro pins, avoiding localized routing congestion and clock buffer blockage.

8. Power Grid (PG) Mesh Planning & IR Drop

A robust power distribution network (PDN) delivers stable VDD and VSS supplies across the entire die without exceeding electromigration (EM) or IR drop limits:

• Power Rings: Core rings routed on top thick metal layers (e.g. M8/M9) carrying global supply current from I/O pads around the core perimeter.
• Power Straps / Mesh: Orthogonal vertical and horizontal metal straps routed on intermediate and upper metal layers to form a low-resistance power grid.
• Standard Cell Follower Rails: Fine horizontal rails on M1 delivering power directly to standard cell VDD and VSS pins.
• Static & Dynamic IR Drop: Static IR drop results from average current through wire resistance (V_drop = I_avg × R_grid); dynamic IR drop results from simultaneous switching currents (L · di/dt noise), mitigated by placing decoupling capacitor (decap) arrays.

9. Placement Optimization Stages & Legalization

Standard cell placement executes in four sequential sub-phases in modern PnR engines:

• Global Placement (Coarse Placement): Determines rough x, y coordinates for every standard cell to minimize total Half-Perimeter Wire Length (HPWL) and spread cell density without respecting site grid discretization.
• High-Fanout Net Synthesis (HFNS): Builds early buffer trees on high-fanout control nets (resets, scan enables, clear pins) to prevent skewed timing cost calculations.
• Placement Legalization: Snaps standard cells to legal placement sites and row orientations without cell overlap, respecting multi-height cell alignment and spacing rules.
• Detailed Placement & Timing Optimization: Swaps cell positions locally, executes gate sizing, and performs logic restructuring to resolve setup and transition violations before Clock Tree Synthesis.

10. Clock Tree Synthesis (CTS) & Skew Balancing

Clock Tree Synthesis distributes low-skew, minimal-latency clock transitions from root sources to hundreds of thousands of sequential register pins:

• Target Skew vs Insertion Delay: Skew targets (typically 50–150 ps) ensure setup and hold predictability, while minimum insertion delay reduces thermal and dynamic power dissipation.
• Clock Routing Rules (NDR): Clock trunks are routed on intermediate-to-thick metal layers (e.g. M5–M7) using Non-Default Routing (NDR) rules—such as Double-Width Double-Spacing (2W2S)—to minimize wire resistance and prevent capacitive crosstalk from adjacent signal nets.
• Clock Mesh vs Tree: High-performance CPU cores utilize hybrid clock meshes to achieve sub-15 ps skew across multi-gigahertz execution units at the cost of higher dynamic power.

11. Detailed Routing, Congestion & DRC Closure

Detailed routing establishes physical metal interconnects and via stacks for all signal and clock nets:

• Global Routing (G-Route): Divides the core canvas into 3D Global Routing Cells (G-Cells) to evaluate wire capacity and predict localized congestion hot spots (hotspot G-cells with demand > 100% capacity).
• Track Assignment: Assigns long straight net segments to specific routing tracks on preferred metal layers.
• Detailed Routing & DRC Fixing: Connects exact cell pins and vias while resolving design rule check (DRC) violations: minimum spacing, minimum area, wide metal spacing rules, notch rules, and antenna diode insertion.

12. Boundary, Endcap, Welltap & Decap Planning

Special non-logical standard cells must be pre-placed before standard cell logic placement:

• Endcap Cells: Placed at the boundaries of standard cell rows and voltage areas to prevent DRC N-well / P-well edge rule violations.
• Well Tap Cells: Placed at regular pitch intervals (e.g. every 20–30 μm) to connect N-well to VDD and P-substrate to VSS, preventing CMOS latchup.
• Decap (Decoupling Capacitor) Cells: Fill empty whitespace with MOS capacitors that provide charge reservoir during rapid switching, suppressing dynamic IR drop.

13. ICC2 / Innovus Implementation Commands

Below is a standard ICC2 floorplanning, CTS, and detailed routing script snippet:

During the routing stage, automated ECO loops optimize wire spreading to reduce coupling capacitance on timing-critical nets while inserting redundant multi-cut vias to maximize manufacturing yield.

14. Congestion Analysis & DRC Signoff Matrix

PnR closure requires evaluating routing congestion maps and signoff DRC reports:

• Global Routing Congestion: Congestion maps highlight routing tracks where demand exceeds available track supply (overflow > 0). Localized hotspots are resolved by adding partial placement blockages (e.g. 70% density bounds) or cell padding.
• Antenna DRC Violations: Long metal wires act as antennas during plasma etching, accumulating static charge that damages gate dielectric oxide. Fixed by inserting reverse-biased antenna protection diodes near receiver input pins or executing metal layer hopping to upper layers.
• Pin Access & Track Alignment: DRC spacing violations at standard cell pins are eliminated by enforcing strict track-aligned cell placement and avoiding abutted cells with opposing pin polarities.

15. Three High-Yield Interview Traps

15. Place & Route Interview FAQs