What is data arrival time?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Data arrival time is the total time the tool calculates from the launch clock edge (time zero) until the data signal actually reaches and switches at the capturing flip-flop's data pin. It's the sum of every delay along the path โ clock tree, the launching flop itself, and the logic in between.
Technical Explanation
The tool builds this number by adding delays in sequence, from the clock source all the way to the capturing pin.
- Clock tree delay first. Before the launch flop even sees its clock edge, the clock signal has already traveled from the clock's source through buffers to reach that flop's clock pin โ this is the clock network latency.
- Clock-to-Q delay next. Once the clock edge hits the launch flop, the flop itself takes a moment to switch its output โ this is an internal delay, taken straight from the cell's library data.
- Combinational and wire delay after that. The signal then passes through logic gates and interconnect wire, each one adding its own delay before the data finally reaches the capturing flop's input pin.
- Setup and hold use different corners for this same sum. For a setup check, the tool computes arrival time using the slowest realistic delays (worst-case process, voltage, temperature). For a hold check, it recomputes the same path using the fastest realistic delays instead โ the two checks never share one arrival-time number.
Common Mistake
- The trap: forgetting that arrival time includes the clock tree delay to the launch flop, not just the logic delay after it.
- It's tempting to think the path "starts" at the flop's Q output, since that's where the data signal itself first appears.
- Leaving out the clock latency term makes every hand calculation of arrival time optimistic โ the real number the tool reports will always be larger once clock network delay is included.
Follow-up Question & Model Response
When you read a report_timing (PT) output, how do you tell the transition time apart from the delay at a given pin?
Candidate Model Response: Each line in the arrival-time section lists an incremental delay column alongside a transition (slew) column. The incremental column is how much time that one cell or wire segment added to the running total โ that's the delay. The transition column is a separate number: how long the signal itself took to swing from low to high (or high to low) at that specific pin. A slow transition often causes the next cell's delay to be larger, but the two numbers describe different things and shouldn't be read as the same quantity.
Practical Example
On a memory controller's critical path, the tool reported a data arrival time of 1.85 ns against a 2.0 ns clock period โ only 0.15 ns of margin. Upsizing the buffer driving the launch flop's output reduced arrival time to 1.62 ns, restoring comfortable setup slack without touching anything else on the path.
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