IntermediateQuestion 1 of 112

Explain the complete setup check for a register-to-register path, including which path delays are used.

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A setup check compares the latest possible data arrival at the capture flop's D pin against the earliest possible required time. Arrival is the launch clock delay plus the launch flop's clock-to-Q delay plus the slowest data path; required is one clock period plus the fastest capture clock delay, minus the flop's setup time and the clock uncertainty margin. The path passes when arrival is less than or equal to required.

Setup check arithmetic: arrival time built from launch clock delay, clock-to-Q and max data path versus required time from period and min capture clock delay — Technical Reference DiagramExplain the complete setup check for a register-to-register path, including which path delays are used.

Technical Reference DiagramExplain the complete setup check for a register-to-register path, including which path delays are used.

Technical Explanation

A setup check on a register-to-register path (FF1 through combinational logic to FF2) asks one question: does data launched by FF1 land at FF2's D pin early enough, before the clock edge that captures it?

Data arrival time is built from three delays added together: the clock's delay reaching FF1's clock pin, FF1's clock-to-Q delay, and the combinational delay from FF1's output to FF2's input. The tool uses the slowest value for each, since setup is a maximum-delay check.
Data required time is the deadline data must beat: the capture edge (one period later by default) plus the clock's delay reaching FF2, minus FF2's setup time (PT) and the clock uncertainty (PT) margin.
Why the pairing is deliberate: the tool matches the slowest data path against the earliest capture edge. If the path survives against the earliest deadline, it survives every other timing of that edge.
Slack is required time minus arrival time; non-negative means met, negative is a setup violation.
Worked numbers: 10 ns period, 0.5 ns launch clock delay, 0.3 ns clock-to-Q, 8.0 ns logic delay, 0.4 ns capture clock delay, 0.5 ns setup time, 0.1 ns uncertainty: arrival = 8.8 ns, required = 9.8 ns, slack = +1.0 ns.

Common Mistake

The Trap: Assuming the setup check always uses the same clock delay value on both ends of the path.

In reality the tool deliberately uses the slowest launch-side clock delay and the fastest capture-side clock delay, because that combination is the hardest one to meet.
An engineer who mentally uses one flat clock-delay number for both sides will compute a slack that is too optimistic and miss a real violation that only shows up once skew is modeled correctly.

Follow-up Question & Model Response

If the capture clock path gets longer after clock tree synthesis, does setup slack get better or worse — and why might the answer surprise you?

Candidate Model Response: Setup slack usually improves when the capture clock path gets longer, because a later capture clock delay pushes the required time later too, giving data more time to arrive. This is the opposite of hold, where a longer capture clock path makes things worse. The surprising part is that clock tree synthesis routinely trades hold margin for setup margin on purpose, since balancing the tree changes both numbers in opposite directions. That is exactly why a design can go from failing setup before CTS to failing hold after it, on the very same path.

Practical Example

Take a 250 MHz core clock (4.0 ns period) feeding two flops, FF_A and FF_B, connected by an 8-bit adder chain. Post-layout report_timing (PT) shows: launch clock delay 0.35 ns, clock-to-Q 0.18 ns, adder delay 3.10 ns, capture clock delay 0.28 ns, library setup time 0.09 ns, and 0.05 ns of clock uncertainty for on-chip variation. Arrival = 0.35 + 0.18 + 3.10 = 3.63 ns. Required = 4.0 + 0.28 − 0.09 − 0.05 = 4.14 ns. Setup slack = 4.14 − 3.63 = +0.51 ns, comfortably met — but if the adder chain grows by one more full-adder stage (about 0.55 ns), the same path fails setup by roughly 40 ps, which is exactly the kind of margin synthesis timing-driven placement is meant to protect.

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