Explain the complete hold check and why a long clock path can cause a hold violation.
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A hold check verifies that data launched by a clock edge does not race through the logic and corrupt the value that same edge is supposed to capture from the previous cycle. Unlike setup, no clock period is added: the tool compares the fastest data arrival against the latest capture edge, so skew and short paths decide the outcome, not the clock frequency.
Technical Explanation
A hold check on FF1 through logic to FF2 asks a same-edge question, not a next-edge one: does data launched by the current clock edge arrive at FF2 so fast that it overwrites the value FF2 still needs to capture from the previous edge?
- No period in the equation. That same-edge framing is what separates hold from setup. The check never adds a clock period, so raising or lowering the clock frequency does not help a hold problem.
- Data arrival time uses the fastest values: the launch clock delay, FF1's clock-to-Q delay, and the shortest combinational delay to FF2. Hold is a minimum-delay check, so data arrives as early as possible โ the worst case for hold.
- Data required time is the same-edge capture time plus the capture clock delay, plus FF2's hold time (PT) โ the window after the edge the input must stay stable โ plus hold uncertainty, using the latest capture clock delay.
- Why a long clock path causes violations: a large capture-side clock delay pushes that same-edge deadline later. New data racing through a short logic path now has more time to arrive before that late edge โ the corruption condition a hold check exists to catch.
- Worked numbers: launch clock delay 0.2 ns, clock-to-Q 0.2 ns, minimum data path 0.4 ns gives arrival = 0.8 ns. A long capture clock delay of 1.0 ns, hold time 0.2 ns, and 0.05 ns uncertainty gives required = 1.25 ns. Hold slack = โ0.45 ns, a violation caused entirely by clock skew.
Common Mistake
The Trap: Believing a hold violation can be fixed by slowing down the clock.
- Because hold never involves the clock period, changing the frequency leaves the violating slack exactly where it was.
- Engineers who reach for a slower clock waste a re-timing run; the real fix is adding delay on the short data path, usually with buffer insertion, which is why hold fixes happen late and are physically expensive to redo.
Follow-up Question & Model Response
Why does fixing a hold violation by inserting a buffer sometimes create a new setup violation on a completely different path?
Candidate Model Response: A hold fix works by adding delay to a short data path, but that same cell often sits on a shared net or drives fanout used by other paths too. If the buffer adds enough delay to a path that was already close to its setup limit, the extra delay can push that other path's arrival time past its required time. This is why hold ECOs are usually done late, one small buffer at a time, with a full setup re-check after each change rather than a batch fix applied blindly across many cells at once.
Practical Example
Consider a scan chain shift register clocked at 500 MHz where two adjacent flops sit at opposite corners of a block. Clock tree synthesis routes flop 2's clock through an extra buffer stage, adding 0.35 ns of insertion delay relative to flop 1. With a minimum data path of only 0.05 ns (a direct flip-flop-to-flip-flop connection with no logic between them), a 0.06 ns hold time, and 0.02 ns hold uncertainty: arrival = 0 + 0.09 + 0.05 = 0.14 ns (using a 0.09 ns clock-to-Q), required = 0.35 + 0.06 + 0.02 = 0.43 ns. Hold slack = 0.14 โ 0.43 = โ0.29 ns, a 290 ps violation that CTS introduced by unevenly balancing the clock tree, not by any change to the logic.
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