BeginnerQuestion 13 of 95

What are launch and capture flip-flops?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

The launch flip-flop is the one whose clock edge sends new data into the path being timed. The capture flip-flop is the one whose clock edge samples and stores whatever arrives. Every register-to-register path the tool reports has exactly one launch flop and one capture flop, even though a single flop often plays both roles for different paths.

A launch flip-flop sending data at time zero and a capture flip-flop checking it against the next clock edge, with the same flop shown playing both roles on adjacent paths — Technical Reference DiagramWhat are launch and capture flip-flops?

Technical Reference DiagramWhat are launch and capture flip-flops?

Technical Explanation

Launch and capture are roles a path assigns to flops, not permanent labels on the flops themselves.

The launch flop starts the clock. Its clock edge (at time zero, in the path's own reference frame) is what kicks off the clock-to-Q delay and sends data on its way through the combinational logic.
The capture flop ends the clock. Its clock edge — one period later for setup, or the very same edge for hold — is the deadline the arriving data gets checked against.
The same physical flop plays both roles, just on different paths. In a pipeline, a flop is normally the capture flop for the stage feeding into it and the launch flop for the stage it feeds out to; the tool tracks each of those as a separate path.
A single flop can even be its own launch and capture flop. A counter that computes count <= count + 1 on every clock edge launches new data and captures the previous result on that same flop.

Common Mistake

The trap: assuming a given flop is permanently either "a launch flop" or "a capture flop" in the design.
Pipelines make this assumption look reasonable at a glance, since most flops sit clearly between an upstream and a downstream stage.
In practice, almost every flop in a multi-stage pipeline is a capture flop for one path and a launch flop for another — the role only makes sense relative to a specific path, not the flop in isolation.

Follow-up Question & Model Response

What happens when the launch flop and the capture flop are driven by different, unrelated clocks?

Candidate Model Response: That path becomes a clock-domain-crossing path, and ordinary setup/hold analysis stops being meaningful if the two clocks are truly asynchronous to each other — there's no fixed phase relationship for the tool to check against. The designer has to tell the tool explicitly how to treat it, usually with set_clock_groups -asynchronous (SDC) to exclude the crossing from normal analysis, or a targeted set_false_path (SDC) if a specific crossing point needs it. The functional correctness of the crossing then has to come from an actual synchronizer circuit, not from timing analysis.

Practical Example

In a pipelined multiplier, the flop labeled Stage_1 launches partial-product data into the adder tree, and the flop labeled Stage_2 captures the resulting sum one cycle later. On the very next cycle, that same Stage_2 flop switches roles and launches its stored sum onward into the final accumulator stage — capture flop for one path, launch flop for the next.

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