BeginnerQuestion 14 of 95

What does set_input_delay do?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

set_input_delay (SDC) tells the tool how much of the clock period was already used up before a signal reached one of the chip's input ports — time spent on the board, in the driving chip's own delay, and in wire flight time. It doesn't add any actual delay inside the chip; it's purely information the tool uses to compute correct arrival times for paths starting at that port.

set_input_delay reserving already-consumed board and driver delay time at a chip input port before the internal budget begins — Technical Reference DiagramWhat does set_input_delay do?

Technical Reference DiagramWhat does set_input_delay do?

Technical Explanation

Without this command, the tool would assume data appears at an input port for free, at time zero — which is never true in practice.

What it models. A signal entering a chip was launched somewhere off-chip, by another device's flip-flop, and travelled across a board trace before reaching the port. set_input_delay gives the tool that already-consumed time, so the input-to-register path gets an honest, correspondingly smaller budget for what's left.
Basic syntax:

# [SDC]  constraints.sdc
  set_input_delay -max 1.2 -clock EXT_CLK [get_ports data_in]
  set_input_delay -min 0.4 -clock EXT_CLK [get_ports data_in]

-max feeds the setup check. It's the slowest realistic external delay, used when the tool computes the worst-case (latest) arrival time at the port.
-min feeds the hold check. It's the fastest realistic external delay, used when the tool computes the best-case (earliest) arrival time for the race condition check.
-clock points at the reference clock the external device used to launch the data — this can be a real design clock, or a virtual clock defined purely for this purpose.
It never inserts a delay buffer. The command is a timing assertion, not a physical change — nothing inside the chip actually gets slower because of it.

Common Mistake

The trap: assuming set_input_delay physically delays the signal inside the chip, the way a buffer would.
It reads like an instruction to "delay this input," which invites the wrong mental model.
It's purely a mathematical statement telling the tool how much time was already spent before the port — misreading it as a physical delay leads to double-counting delay that already exists elsewhere in the model.

Follow-up Question & Model Response

Why does set_input_delay need both a -max and a -min value instead of one number?

Candidate Model Response: Because setup and hold need opposite worst cases. Setup wants to know the latest data could possibly arrive, so -max supplies the slowest realistic external delay. Hold wants to know the earliest data could possibly arrive, so -min supplies the fastest realistic external delay. Using one shared value for both checks would either be too pessimistic for one of them or, worse, not conservative enough — the two directions genuinely need different numbers.

Practical Example

For an RGMII Ethernet receive interface running at 125 MHz (an 8 ns period), set_input_delay -max 2.8 -clock RX_CLK [get_ports rx_data*] reserves 2.8 ns for PHY-side and board-trace skew, leaving 5.2 ns of the 8 ns period for the signal to settle inside the chip before the first internal flop needs it.

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