IntermediateQuestion 14 of 112

What are max_capacitance limits, and is max_fanout also covered by these library references?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

max_capacitance (LIB) is a design-rule ceiling, specified per pin in the standard cell library, on the largest output load — the total capacitance of the wire plus whatever it drives — a cell is allowed to drive. Like max_transition, exceeding it is a hard DRC failure regardless of the path's timing slack. max_fanout (LIB) is a related but separate library attribute limiting the number of pins driven, not the electrical load directly.

max_capacitance electrical load ceiling on a long wire compared against max_fanout pin-count limit on a short, widely-branched net driven by the same library cell — Technical Reference DiagramWhat are max_capacitance limits, and is max_fanout also covered by these library references?

Technical Reference DiagramWhat are max_capacitance limits, and is max_fanout also covered by these library references?

Technical Explanation

What load capacitance is. Every cell output drives some combination of interconnect wire and the input pins of whatever it fans out to; all of that together is its load capacitance. A cell characterized for a light load will behave incorrectly, or simply too slowly, if asked to drive far more capacitance than it was built for.
What max_capacitance limits. The library specifies, per output pin, the largest total load capacitance that cell is allowed to drive while staying within its characterized and guaranteed behavior. max_capacitance (LIB) is exactly that ceiling, listed in the .lib file alongside max_transition.
Why it's a DRC, not a slack check. Exactly like max_transition, this is a fixed limit compared against a measured value — it has nothing to do with clock periods, required times, or slack, and a path with excellent setup margin can still violate it.
What max_fanout measures instead. max_fanout (LIB) is a separate library attribute that counts the number of pins a cell's output connects to, not the electrical capacitance those pins represent. It is a coarser, load-independent proxy, historically used before extraction-based capacitance numbers were reliably available at every design stage.
Why both can matter on the same net. A net can pass a fanout check (few enough pins) while still failing max_capacitance, if those few pins happen to sit on a very long or wide wire; conversely a net with many small pins close together might pass max_capacitance while tripping a fanout limit meant to catch excessive logical loading for other reasons, such as synthesis-stage estimation before real parasitics exist.

Common Mistake

The Trap: Treating max_fanout as a stand-in for max_capacitance because both are library-specified load limits.

Fanout counts connections, not electrical load, so a low-fanout net can still be electrically overloaded if it is unusually long or wide.
Relying on fanout checks alone at layout stage, after real parasitics exist, misses exactly the capacitance violations that only extraction can reveal.

Follow-up Question & Model Response

Why would a synthesis tool rely on max_fanout at all, if max_capacitance is the more electrically accurate limit?

Candidate Model Response: During synthesis, before placement and routing exist, the tool has no real wire lengths to compute actual capacitance from, so a fanout count is a usable, load-independent proxy for roughly how much a net will need to drive. It is a cheap, early estimate that catches grossly over-loaded nets before real parasitics are available. Once layout produces extracted RC data, max_capacitance becomes the accurate, authoritative check, and max_fanout mostly stops adding new information beyond what capacitance and transition checks already catch.

Practical Example

A 2-input NAND cell in a 28nm library is characterized with max_capacitance of 0.08 pF and max_fanout of 20 on its output pin. In one block, that gate drives only 4 downstream pins (well under the fanout limit) but routes across a long 900 micron wire with 0.095 pF of extracted wire capacitance alone — a max_capacitance violation of 0.015 pF despite the low fanout. In a different block, the same gate cell type drives 22 very small, closely spaced buffer inputs on a short net, tripping the max_fanout limit at 22 pins while the total extracted capacitance, only 0.06 pF, stays comfortably under the max_capacitance ceiling — two different violations from two different mechanisms on the same cell type.

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