What does set_output_delay do?

Short Answer

set_output_delay (SDC) tells the tool how much time must be left over, after a signal leaves the chip's output port, for the board and the receiving device's own setup or hold needs. Like set_input_delay, it's a timing assertion the tool uses for its math, not a delay it physically inserts.

Technical Explanation

This command constrains the far end of the chip boundary, the mirror image of what set_input_delay does at the near end.

• What it models. A downstream chip on the board needs the signal to arrive before its own capturing clock edge, and to stay stable a bit after. set_output_delay reserves that needed time on the far side, so the internal path budget shrinks by exactly that amount.
• Basic syntax:

# [SDC]  constraints.sdc
  set_output_delay -max 1.4 -clock EXT_CLK [get_ports data_out]
  set_output_delay -min -0.2 -clock EXT_CLK [get_ports data_out]

• -max feeds the setup check on the reg2out path — it's the time the downstream device needs before its own clock edge, subtracted from the internal budget.
• -min feeds the hold check and can legitimately be negative, if the interface specification calls for it — the sign has to match how the downstream device's own hold requirement was defined.
• A virtual clock covers a receiver with no on-chip clock reference. If the downstream device runs off its own separate oscillator, defining a virtual clock with create_clock (no port or pin attached) and referencing it here gives the tool a timing frame for that interface without pretending the external clock is part of this design.

Follow-up Question & Model Response

How does set_output_delay interact with a virtual clock?

Candidate Model Response: The virtual clock stands in for a clock that exists on the receiving device but has no pin or port anywhere in this design. Defining it with create_clock and no attached object gives the tool a named timing reference with a period and phase, and referencing that virtual clock's name in set_output_delay lets the tool compute a correct required time at the output port — exactly as if the real external clock had been visible to the design, without ever pretending the design actually contains it.