What is timing signoff?

Short Answer

Timing signoff is the final checkpoint where a design must show zero setup and hold violations, clean design-rule checks, and full path coverage across every required corner, before the layout is released for manufacturing.

Technical Explanation

Signoff is the point where estimates and workarounds stop being acceptable, because after this the design becomes a fixed, expensive photomask.

• Setup clean everywhere it matters: zero setup violations across every slow-corner scenario the design is expected to run at.
• Hold clean everywhere it matters: zero hold violations across every fast-corner scenario, since hold failures cannot be masked by clock frequency at all.
• Design rules clean: no transition or capacitance limit violations left anywhere in the design, since those undermine the accuracy of the delay numbers themselves.
• Full path coverage: check_timing (PT) reporting no unconstrained endpoints, so a clean report actually reflects a fully checked design rather than one with silent gaps.
• Consistency with the original design intent: a formal equivalence check confirming the final, timed netlist still implements the same logic as the golden source design, so no functional change slipped in during all the timing fixes.

Follow-up Question & Model Response

What is an ECO, and why does it usually happen right at the edge of signoff rather than earlier?

Candidate Model Response: An ECO, or Engineering Change Order, is a small, surgical netlist edit — resizing a cell, inserting a buffer, or swapping a cell's threshold voltage — made late in the flow to close a remaining violation without redoing placement or routing. It shows up near signoff because that is the first point where the design has real, extracted timing data accurate enough to know exactly which cells need to change. Doing the same fix earlier, on estimated pre-layout numbers, risks fixing a problem that later shifts or disappears once the real layout exists.