What is the difference between an ideal clock and a propagated clock?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
An ideal clock reaches every register at the same instant, with no physical clock tree modeled yet. A propagated clock is traced through the design's real clock buffers and wires, so it carries the true insertion delay and skew that physical clock tree synthesis actually produced.
Technical Explanation
Early in the flow the clock tree does not exist yet, so the tool has nothing physical to trace it through — that gap is exactly what an ideal clock stands in for.
- Ideal clock: before clock tree synthesis, the tool assumes the clock edge reaches every register at the same moment, or with a flat estimated latency set by the designer.
- Modeling the unknown skew: since no real clock tree exists yet, any expected future skew is budgeted as a margin using
set_clock_uncertainty(SDC), not measured. - Propagated clock: once
set_propagated_clock(SDC) is applied, the tool walks the actual synthesized buffers and wires from the clock source to each register's clock pin, adding up their real delays. - What propagation reveals: real skew between registers, and the true common clock path shared by a launch and capture pair, both of which only exist once there is a physical tree to measure.
- Why the switch matters: running signoff with clocks still ideal after the tree is built means the tool is checking against a clock network that no longer resembles the real chip.
Common Mistake
The Trap: Forgetting to switch clocks to propagated after clock tree synthesis is complete.
- Left ideal, the tool keeps assuming a clock network that no longer matches the physical design.
- Every signoff slack number computed that way is meaningless, since it is timed against a clock tree that was never actually built that way.
Follow-up Question & Model Response
Why can on-chip variation derating not be applied accurately while a clock is still ideal?
Candidate Model Response: On-chip variation derating depends on how many buffer stages and how much physical distance a clock edge travels, since deeper or longer clock paths accumulate more variation. An ideal clock has no real stages or distance to measure that from, so any derate applied to it is a guess rather than a value tied to the actual tree. Once the clock is propagated, the tool can apply derating stage by stage along the real path, including giving credit back for the portion of the path two registers' clocks share in common.
Practical Example
A block signed off with ideal clocks shows 0.55 ns of setup slack on its worst path. After clock tree synthesis, the same path re-timed with propagated clocks shows only 0.12 ns of slack, because the real clock tree added measurable skew between the launch and capture registers that the ideal model had assumed away.
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