IntermediateQuestion 10 of 112

What is the difference between asynchronous, logically_exclusive, and physically_exclusive clock groups?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

set_clock_groups (SDC) classifies how two clock domains relate for timing purposes. -asynchronous marks clocks with no fixed phase relationship, so paths between them are not meaningfully timed. -logically_exclusive marks clocks that never operate at the same time functionally, though they may still coexist physically on the die. -physically_exclusive goes further, asserting the clocks also cannot electrically interfere with each other.

set_clock_groups relationships compared: asynchronous clocks with no fixed phase, logically exclusive clocks selected by a mux, and physically exclusive clocks that cannot electrically interfere — Technical Reference DiagramWhat is the difference between asynchronous, logically_exclusive, and physically_exclusive clock groups?

Technical Reference DiagramWhat is the difference between asynchronous, logically_exclusive, and physically_exclusive clock groups?

Technical Explanation

Why clock groups exist at all. Without grouping, the tool checks every pair of clocks for timing paths between them by default, including ones with no meaningful relationship. set_clock_groups (SDC) tells the tool how a pair of clocks actually relate.
-asynchronous. Marks clocks with no fixed phase relationship at all — two independent oscillators, say. The tool stops computing setup/hold slack between them; this is the group used for a genuine clock domain crossing, alongside proper synchronizer logic.
-logically_exclusive. Marks clocks the design guarantees will never be active at the same time — two clocks sharing a physical pin, selected by a mux, where only one toggles in a given mode. Timing is excluded because a functional condition prevents both operating together, even though nothing stops them physically coexisting if that condition were ever violated.
-physically_exclusive. A stronger claim: the clocks also cannot electrically interfere with each other, useful when the physical structure itself, not just a mode signal, guarantees separation.
Why the distinction matters. -logically_exclusive and -asynchronous rely on a functional assumption rather than a physical fact, so they carry the same risk as a false path: if the assumption is wrong, the excluded interaction is never checked.

Common Mistake

The Trap: Using -logically_exclusive for two clocks that are merely usually mutually exclusive rather than provably always so.

If the mux select signal that is supposed to guarantee exclusivity can glitch or briefly select both inputs during a transition, the tool still trusts the assertion completely and never re-checks it.
The result is the same class of silent gap as an over-broad false path: a clean signoff report that hides a real, unverified interaction between the two clocks.

Follow-up Question & Model Response

Why would you ever choose -asynchronous over -logically_exclusive for two clocks that, in your design, never actually run at the same time?

Candidate Model Response: If two clocks never run simultaneously purely by usage model, but do have some fixed phase relationship whenever they are both active, treating them as logically exclusive is the tighter and more accurate choice, since it reflects the real constraint. But if the two clocks come from genuinely independent, free-running sources with no phase relationship at all, calling them logically exclusive would be inaccurate — they are asynchronous by construction, not merely excluded by a mode signal. Choosing asynchronous over logically_exclusive in that case is about matching the grouping to the actual physical relationship, not just to whether they happen to overlap in time.

Practical Example

A chip has a 100 MHz main clock (CLK) and a 50 MHz clock divider output (CLK_DIV2) generated from it, plus a separate 32 kHz always-on watchdog clock (CLK_WD) from an independent on-chip oscillator. Because CLK_DIV2 is derived from CLK with a fixed phase relationship, it is never grouped as exclusive with CLK at all — it is timed normally as a generated clock. CLK_WD, however, has no phase relationship to CLK whatsoever, so the SDC applies set_clock_groups -asynchronous -group [get_clocks CLK_WD] -group [get_clocks {CLK CLK_DIV2}], which removes the meaningless cross-domain slack numbers that would otherwise appear between the watchdog and the main clock domain, while leaving CLK and CLK_DIV2 fully and correctly timed against each other.

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