What are the major input files STA needs to run (netlist, library, SDC, parasitics)?

Short Answer

STA needs four files to run: a gate-level netlist describing what is connected to what, Liberty timing libraries describing how each cell behaves, an SDC file stating the timing intent, and — for post-layout accuracy — a SPEF file with extracted wire parasitics.

Technical Explanation

Take away any one of these four and the tool either cannot run at all, or runs with a guess standing in for real data.

• Gate-level netlist: the structural description of instances, ports, and exactly which pin connects to which — the tool's map of the circuit.
• Liberty timing libraries: the delay, slew, and pin-capacitance tables for every cell used, characterized separately for each corner the design is checked against.
• SDC constraints: the clocks, I/O timing, and exceptions that define what the design is actually supposed to meet — without this, the tool has a circuit but no target to check it against.
• SPEF parasitics: the extracted wire resistance and capacitance for every net, needed for accurate post-layout wire delay rather than a pre-layout estimate.
• Optional but common additions: variation tables for on-chip variation derating, and power-intent files where multiple voltage domains affect timing.

Follow-up Question & Model Response

What happens if a cell instance in the netlist has no matching entry in any loaded Liberty library?

Candidate Model Response: The tool cannot compute any delay for a cell it has no timing model for, so it reports an unresolved reference and effectively treats that instance as a black box. Every path passing through that cell becomes unconstrained rather than checked, which is exactly the kind of silent gap check_timing (PT) is meant to catch before anyone trusts the resulting slack report. The usual cause is a missing or mismatched library revision, so I would check that every cell in the netlist maps to a library the run actually loaded.