BeginnerQuestion 12 of 50

What are the different states a power domain can be in (fixed voltage, switchable, DVS, DFS, DVFS)?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A domain can be fixed (one voltage, always on), switchable (power can be cut), DVS (voltage changes at run time), DFS (clock frequency changes) or DVFS (voltage and frequency change together). Each type adds its own hardware and verification. The more a domain can change, the more crossings and states you have to check.

Table with rows fixed, switchable, DVS, DFS and DVFS, columns "what changes" (nothing, supply on or off, voltage, frequency, both) and "what it needs" (nothing extra; switch, isolation, retention, AO control; level shifters and multi-voltage timing; clock divider or PLL; sequencing controller), one example per row. — Technical Reference DiagramWhat are the different states a power domain can be in (fixed voltage, switchable, DVS, DFS, DVFS)?

Technical Reference DiagramWhat are the different states a power domain can be in (fixed voltage, switchable, DVS, DFS, DVFS)?

Technical Explanation

Fixed: one voltage, always on; example, the always-on controller. Needs nothing extra beyond normal signoff.
Switchable: the supply can be cut; example, a GPU. Needs power switches, isolation on outputs, retention if state matters, always-on control.
DVS (dynamic voltage scaling): voltage moves between levels; example, a DSP at 0.9 V or 1.1 V. Needs level shifters valid at every level.
DFS (dynamic frequency scaling): only the clock changes; example, a bus fabric. Needs a glitch-free clock switch or divider.
DVFS: both change together; example, a CPU cluster. Raise V before raising f, and lower f before lowering V.
Types combine: a switchable domain can also be DVS, and then it needs both sets of hardware.
Each voltage level adds a timing corner, and each on/off combination adds a power state to verify.

Common Mistake

The Trap: Treating a DVS domain as fixed voltage for level-shifter decisions.

A crossing that is equal-voltage at 1.1 V becomes low-to-high at 0.9 V, and without a level shifter the receiver sees a weak high and leaks or fails.
Check every crossing of a DVS domain at every voltage level it can reach, not only at nominal.

Follow-up Question & Model Response

"Why must voltage go up before frequency on a DVFS step up?"

Candidate Model Response: At the new, higher frequency the logic needs the extra drive that only the higher voltage gives. If the clock rises first, paths fail setup for the time the voltage is still ramping. Going down, you lower the clock first for the same reason. The rule keeps every instant inside a voltage and frequency pair that was signed off.

Practical Example

Design Scenario: (illustrative) In MYCHIP, PD_MYCHIP is fixed at 1.0 V, PD_CPU is fixed at 0.9 V, PD_COP is switchable with retention, and PD_DSP is DVS between 1.1 V and 0.9 V from an external regulator. PD_DSP to PD_MYCHIP crossings are high-to-low at 1.1 V and low-to-high at 0.9 V, so the level shifter must handle both. Check the verification load: two PD_DSP voltage levels times PD_COP on and off gives at least four combinations to cover.

Low-Power & UPF Handbook