How do you decide between placing a level shifter in "self" vs "parent" location?

Short Answer

Pick the side where the shifter can get both supplies cheaply: its row rail gives one supply and a secondary pin must reach the other. Self puts the cell inside the domain whose port is shifted; parent puts it in the surrounding domain. For MYCHIP, up-shifters on PD_CPU outputs usually sit in the parent, and down-shifters on PD_CPU inputs sit in self.

Technical Explanation

• Self: the cell sits in the shifted domain, here PD_CPU, on its VDD0p9 row rail.
• Parent: the cell sits in the parent domain, here PD_MYCHIP, on its VDD1p0 row rail. It is an error on a top-module port.
• Supply rule: ICC2 says you must make the needed supplies available at the location you choose.
• Which pin is secondary depends on the library cell. Check it with report_mv_lib_cells (ICC2) before choosing.
• Down-shifters are often single-rail cells powered from the output side, so self in PD_CPU needs no extra strap. Confirm this for your library.
• Routing: with parent, the unshifted 0.9 V net crosses the boundary, and many sinks can share one shifter at the port.
• Secondary straps need create_secondary_pg_placement_constraints (ICC2) so dual-rail shifters land only where the strap exists.

# [UPF]  mychip.upf
set_level_shifter FROM_PD_CPU_LST -domain PD_CPU -applies_to outputs -rule low_to_high -location parent
set_level_shifter TO_PD_CPU_LST -domain PD_CPU -applies_to inputs -rule high_to_low -location self
# [ICC2]  icc2_shell
report_mv_lib_cells -verbose
create_mv_cells
check_mv_design

What To Check

• For each shifter cell, you know which supply comes from the row and which from a secondary pin.
• That secondary supply has a strap in the host voltage area.
• Up-shifters on outputs do not sit in a domain that switches off while the receiver is on.
• The strategy fixes -location when written, because ICC2 will not accept it with -update.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Up-shifters sit in PD_MYCHIP rows within reach of the VDD0p9 strap, down-shifters in PD_CPU rows, and check_mv_design is clean.
• Suspicious (illustrative): Dual-rail shifters placed far from any strap of their secondary supply, which will need long PG routes.
• Hard stop: A shifter whose second supply is not available in its host domain, or -location parent on a top-module port.

What The Interviewer Is Testing

• Do you think about the rails a cell needs, not just the logical side of the boundary?
• Do you check the library cell before picking a location?

Follow-up Question & Model Response

"What changes if PD_CPU could shut down?"

Candidate Model Response: Then its outputs also need isolation, and the usual answer is an enable level shifter placed in the always-on parent. A shifter left in self would sit on a rail that disappears, exactly when its output must hold a safe value. The parent also keeps the always-on control and supply out of the switched area. PD_CPU in MYCHIP never switches, so plain shifters are enough there.