IntermediateQuestion 8 of 60

How do you write a level-shifter strategy with set_level_shifter, and what do its key options control?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

Short Answer

set_level_shifter (UPF) tells the tool which ports of a domain get level shifters, for which voltage direction, and in which domain the cell sits. Low-to-high crossings always need a shifter; high-to-low ones depend on the library and the voltage gap, which is what -rule and -threshold let you filter. Without any strategy, ICC2 still inserts shifters from the voltages in the power states.

Technical Reference DiagramHow do you write a level-shifter strategy with set_level_shifter, and what do its key options control?

Technical Explanation

  • -domain names the domain whose ports are shifted; copy the option name exactly, since a misspelled variant fails to load.
  • -applies_to inputs, outputs or both, narrowed with -elements or filtered with -source and -sink.
  • -rule low_to_high, high_to_low or both (default both) keeps the strategy to one direction.
  • -threshold applies the strategy only where the voltage difference exceeds the value; the 1801-2015 default is 0.
  • -location: 1801-2015 defaults to self, while the ICC2 MV guide lists automatic as default. Set it explicitly.
  • -input_supply and -output_supply name the supply sets for each side; -no_shift blocks insertion on listed ports.
  • You cannot combine -location with -update in ICC2, so fix the location when you first write the strategy.
# [UPF]  mychip.upf
set_level_shifter FROM_PD_CPU_LST -domain PD_CPU -applies_to outputs -rule low_to_high -location parent
set_level_shifter TO_PD_CPU_LST -domain PD_CPU -applies_to inputs -rule high_to_low -location self
# [ICC2]  icc2_shell
create_mv_cells
check_mv_design
analyze_mv_design -level_shifter -through U_CPU/dout

What To Check

  • Every PD_CPU output into a 1.0 V domain has a low-to-high shifter.
  • High-to-low crossings are covered or deliberately excluded with a library-backed reason.
  • Each strategy states -location explicitly.
  • The chosen location has both supplies available.

Command Checks & Actions

UPF (design.upf)set_level_shifter FROM_PD_CPU_LST -domain PD_CPU -applies_to outputs -rule low_to_high -location parent

Shift PD_CPU outputs up to 1.0 V in the parent domain

ICC2 (icc2_shell)create_mv_cells

Insert shifters from the strategies before placement

ICC2 (icc2_shell)check_mv_design

Report missing or wrongly oriented level shifters

ICC2 (icc2_shell)analyze_mv_design -level_shifter -through U_CPU/dout

Explain why no shifter was inserted on one net

Healthy, Suspicious & Hard-stop Results

  • Healthy (illustrative): check_mv_design reports no missing level shifters, and every PD_CPU output shows an up-shifter.
  • Suspicious (illustrative): A high-to-low crossing has no shifter and no written reason for skipping it.
  • Hard stop: A 0.9 V to 1.0 V output drives PD_MYCHIP with no shifter, or load_upf rejects a misspelled -domain option.

Common Mistake

The Trap: Writing -rule low_to_high on the inputs of PD_CPU, which is actually the lower-voltage side.

  • The filter matches no port, so the real 1.0 V to 0.9 V inputs are left to other strategies or automatic insertion instead of your intent.

What The Interviewer Is Testing

  • Do you know low-to-high is mandatory and high-to-low is conditional?
  • Can you explain -rule and -threshold as filters rather than cell choices?

Follow-up Question & Model Response

"Why is a low-to-high shifter mandatory while high-to-low sometimes is not?"

Candidate Model Response: A 0.9 V high driving a 1.0 V gate may not turn its PMOS fully off, so the receiver leaks and switches slowly. Going the other way, a 1.0 V signal into a 0.9 V gate turns it fully on and off. Whether the input can tolerate the higher voltage is a library and reliability question. So you skip high-to-low shifters only when the library says the cell is safe at that gap.

Practical Example

Design Scenario: (illustrative) PD_CPU runs at 0.9 V inside PD_MYCHIP at 1.0 V. FROM_PD_CPU_LST shifts every PD_CPU output up and places the cells in PD_MYCHIP. TO_PD_CPU_LST shifts inputs down inside PD_CPU. If the library allowed a 0.1 V over-drive on 0.9 V inputs, you could add -threshold 0.15 to TO_PD_CPU_LST and it would insert nothing, while FROM_PD_CPU_LST keeps its up-shifters.

Low-Power & UPF Handbook

Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.

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