What isolation placement locations are available (self, parent, fanout, automatic), and how do you choose between them?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
For set_isolation (UPF), IEEE 1801-2015 lists four locations: self (the default), parent, other and fanout; automatic is a set_level_shifter (UPF) value in ICC2, not an isolation one. The location decides which domain hosts the cell, and therefore which rail its row gives it. Choose the site where the isolation supply is already on, so you avoid a dual-rail cell and a secondary strap inside a switched area.
Technical Explanation
- self: the cell sits inside the domain being isolated. In a shutdown domain its row rail dies, so it needs a dual-rail cell fed from SS_AON.
- parent: the cell sits in the parent domain. It is an error on a top-module port or a lower-boundary port.
- other: parent domain for an upper-boundary port, child domain for a lower-boundary port.
- fanout: a cell in each fanout domain, at the port closest to the receiver. ICC2 needs
-source,-sinkor-diff_supply_onlywith it. - ICC2 also forbids
-isolation_power_netwith fanout; parent and self accept it. - Why it matters: ICC2 picks single-rail cells where the host rail stays on and dual-rail where it switches, and warns on the wrong kind.
- Parent is the usual choice for shutdown outputs; fanout helps when sinks sit in domains with different supplies or clamp needs.
# [UPF] mychip.upf
set_isolation ISO_COP_PAR -domain PD_COP -elements {U_COP/req} -applies_to outputs -isolation_supply SS_AON -clamp_value 0 -isolation_signal U_PC/ISE -isolation_sense high -location parent
set_isolation ISO_COP_FAN -domain PD_COP -applies_to outputs -sink SS_CPU -isolation_supply SS_CPU -clamp_value 0 -isolation_signal U_PC/ISE -isolation_sense high -location fanout
# [ICC2] icc2_shell
create_mv_cells
report_mv_cells
check_mv_design -isolationWhat To Check
- The host domain of each isolation cell has the isolation supply available.
- No single-rail isolation cell sits in a shutdown area.
- Fanout strategies carry a -source, -sink or -diff_supply_only filter.
- Parent is not used on a top-module port.
Command Checks & Actions
set_isolation ISO_COP_PAR -domain PD_COP -elements {U_COP/req} -applies_to outputs -isolation_supply SS_AON -location parentPlace the cell in PD_MYCHIP, where VDD1p0 stays on
create_mv_cellsInsert isolation cells at the chosen locations
report_mv_cellsList inserted cells and the domain that holds each one
check_mv_design -isolationReport rail violations, such as a single-rail cell in a shutdown domain
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): Every PD_COP output isolation cell sits in PD_MYCHIP rows as a single-rail cell on SS_AON, and
check_mv_designis clean. - Suspicious (illustrative): Self-located cells in PD_COP mapped to dual-rail cells: legal, but each needs an SS_AON secondary strap inside the switched area.
- Hard stop: A single-rail isolation cell in PD_COP (rail violation warning) or a fanout strategy rejected for missing a -sink filter.
Common Mistake
The Trap: Leaving PD_COP output isolation at the default self location without checking which cells the library offers.
- If only single-rail cells exist, ICC2 inserts them inside PD_COP with a warning, and they lose power when the switch opens.
What The Interviewer Is Testing
- Do you know the four 1801-2015 locations and which one is the default?
- Can you link location to rail type and secondary PG routing?
Follow-up Question & Model Response
"When would you pick self even for a shutdown domain?"
Candidate Model Response: When the block is hardened separately and must carry its own isolation, so the parent cannot host the cells. A reusable IP delivered with its own UPF is the usual case. You then budget dual-rail isolation cells and an always-on secondary strap inside the switched voltage area. It costs routing, but the block stays self-contained at integration.
Practical Example
Design Scenario: (illustrative) PD_COP drives req into PD_MYCHIP and data to two sinks in PD_CPU. ISO_COP_PAR puts the req cell in PD_MYCHIP, where the VDD1p0 row rail is always on, so a single-rail cell works. ISO_COP_FAN puts one cell next to each PD_CPU sink, powered by SS_CPU at 0.9 V. Had you left req at self, the cell would sit on VDD1p0_SW and need a dual-rail cell plus an SS_AON strap across PD_COP.
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