ExpertQuestion 22 of 50

How do you size a MTCMOS sleep transistor (header/footer), and what happens if it's undersized or oversized?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Size the switch bank so its combined on-resistance, times the peak current of the domain, stays inside the IR-drop budget of the virtual rail. That sets a minimum switch count; the upper limit comes from area, the switches own off-state leakage and wake-up rush current. Undersize it and every path in the domain runs slow; oversize it and you pay leakage, area and a larger in-rush spike.

Schematic of PD_COP fed from VDD1p0 through 170 parallel PMOS header switches (HEADER_X4, R_on 15 each) onto VDD1p0_SW, with the block drawn as a 300 mA current sink and the 26.5 mV drop across the switch bank labelled against a 27 mV budget. — Technical Reference DiagramHow do you size a MTCMOS sleep transistor (header/footer), and what happens if it's undersized or oversized?

Technical Reference DiagramHow do you size a MTCMOS sleep transistor (header/footer), and what happens if it's undersized or oversized?

Technical Explanation

Series resistance: a header (PMOS on VDD) or footer (NMOS on VSS) sits in series with the whole domain, so the block sees VDD minus I × R_on.
Parallel bank: N identical switches give R_eff = R_on / N, so the IR target sets the minimum N.
Header cost: PMOS carries less current per width than NMOS, so a header needs more width for the same R_on.
Undersized: VDD1p0_SW sags under load and every gate slows; STA with an ideal supply misses it unless IR-aware timing is run.
Oversized: more area, more switch leakage when the domain is off, and a faster, larger in-rush spike at wake-up.
ICC2 sizing: after a voltage drop run, size_power_switches -max_irdrop (ICC2) swaps same-footprint switch cells toward the target; check the man page for your release.
R_on source: set_power_switch_resistance (ICC2) sets the R_on limit per library cell, taken from the switch model file.

# [ICC2]  icc2_shell
analyze_rail -voltage_drop static -nets {VDD1p0 VDD1p0_SW VSS}
set_power_switch_resistance lp_lib/HEADER_X4 0.015
size_power_switches -max_irdrop 0.027
report_power_switch_resistance -verbose

Formula Or Decision Rule

Bank resistance: R_eff = R_on / N
IR rule: I_peak × R_eff ≤ ΔV_budget, so N ≥ I_peak × R_on / ΔV_budget
Leakage check: N × I_off,switch must stay far below the leakage saved by gating the domain.

What To Check

Peak current comes from a realistic worst activity window, not the average.
The IR budget for the switch is agreed separately from the grid budget.
Switches are spread across the domain, not clumped at one edge.
Off-state leakage of the bank is small against the leakage it removes.

Command Checks & Actions

ICC2 (icc2_shell)analyze_rail -voltage_drop static -nets {VDD1p0 VDD1p0_SW VSS}

Measure the drop on the real and virtual rails

ICC2 (icc2_shell)set_power_switch_resistance lp_lib/HEADER_X4 0.015

Give the sizer the 15 ohm R_on limit, written in library resistance units as the guide example does

ICC2 (icc2_shell)size_power_switches -max_irdrop 0.027

Swap switch cells toward a 27 mV effective drop target

ICC2 (icc2_shell)report_power_switch_resistance -verbose

List switch cells, their R_on and instance counts

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Worst drop across the PD_COP switch bank is 26.5 mV against a 27 mV budget.
Suspicious (illustrative): The average drop meets 27 mV but a cluster near the macro edge reaches 35 mV.
Hard stop: The drop exceeds 27 mV on most of PD_COP, or size_power_switches reports no cell that can meet the target.

Common Mistake

The Trap: Sizing the bank from average current instead of the peak switching window.

The rail passes a static check but droops during bursts, and those paths fail in silicon while STA shows positive slack.

What The Interviewer Is Testing

Can you turn an IR budget into a switch count?
Do you know both failure directions, not just undersizing?

Follow-up Question & Model Response

"Why not just add 50 percent more switches to be safe?"

Candidate Model Response: Because every extra switch leaks when the domain is off, and that eats into the reason you gated it. More switches also charge the virtual rail faster, so peak in-rush current rises and can pull down always-on neighbours. They cost area and routing near the straps. Size to the budget with a measured margin, then check in-rush separately.

Practical Example

Design Scenario: (illustrative) PD_COP runs at 1.0 V on VDD1p0_SW with a 300 mA peak. The switch budget is 27 mV (2.7 percent), so R_eff must be at most 0.09 ohm. With HEADER_X4 at 15 ohm, N ≥ 15 × 0.3 / 0.027 = 167, so the team places 170. That gives 15 / 170 = 0.088 ohm and a 26.5 mV drop. Cell names and values are illustrative, not foundry data.

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