What is the architectural difference between header and footer power switches, and when would each be used?

Short Answer

A header is a PMOS switch between the real VDD and the block virtual VDD; a footer is an NMOS switch between the block virtual VSS and the real VSS. Footers are smaller for the same on-resistance because NMOS carries more current per width, but headers keep one shared ground, which multi-voltage designs depend on. Most SoCs pick headers, and the library declares either kind with define_power_switch_cell (UPF).

Technical Explanation

• Header: PMOS between VDD and virtual VDD; every domain keeps the shared VSS.
• Footer: NMOS between virtual VSS and VSS; every domain keeps its real VDD.
• Area: NMOS mobility is roughly twice PMOS, so a footer needs about half the width for the same on-resistance (illustrative ratio).
• Clean rail: headers keep ground common across domains, so shifters and isolation cells reference one VSS.
• Bounce: a footer lifts virtual VSS by I×R_on under load, so logic lows sit above true ground and crossing noise margin shrinks.
• Body effect: logic with its source on the virtual rail and its well on the real rail sees reverse bias, which slows it slightly as the rail sags.
• Declare the cell with define_power_switch_cell (UPF): -power_switchable and -power for a header, -ground_switchable and -ground for a footer.

# [UPF]  library power intent
define_power_switch_cell -cells {HEADER_X4} -type header -stage_1_enable !SLEEP -stage_1_output SLEEPOUT -power_switchable VDDV -power VDD
define_power_switch_cell -cells {FOOTER_X4} -type footer -stage_1_enable EN -stage_1_output ENOUT -ground_switchable VSSV -ground VSS
# [UPF]  mychip.upf
map_power_switch COP_SW -domain PD_COP -lib_cells {HEADER_X4}
# [ICC2]  icc2_shell
report_mv_lib_cells
report_power_switch_resistance -verbose

What To Check

• The switch cell has the right -type and enable polarity for its pins.
• Header designs keep one common VSS; footer designs model virtual VSS in IR and timing.
• On-resistance per cell times cell count meets the domain IR budget.
• map_power_switch (UPF) names a cell of the chosen type.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): 440 HEADER_X4 cells give PD_COP about 27 mV of drop at 60 mA, inside a 30 mV budget.
• Suspicious (illustrative): A footer variant shows 40 mV of virtual VSS rise at peak current, most of the low-side noise margin at the crossings.
• Hard stop: The header is declared with an inverted enable, so the modeled on condition is the opposite of the real PMOS gate behaviour.

What The Interviewer Is Testing

• Whether you argue header vs footer from area, noise and multi-voltage needs, not only definitions.
• Whether you know how a switch cell is declared in UPF without invented options.

Follow-up Question & Model Response

"Why do most multi-voltage SoCs use headers even though footers are smaller?"

Candidate Model Response: Multi-voltage designs already have several VDD rails, and they rely on one shared VSS so every signal swings from the same ground. Headers keep that ground and switch only the supply side. Footers would add a virtual ground per domain and give every crossing a different ground reference. The PMOS area penalty is usually cheaper than that verification and noise cost.