What is Dynamic Voltage and Threshold Scaling (DVTS / Vth-hopping), and how does it combine two leakage/performance levers at once?

Short Answer

DVTS changes the supply voltage and the transistor threshold together at run time: VDD through the regulator, Vt through body bias on the wells. At a low-performance point it lowers VDD and applies reverse bias to raise Vt and cut leakage; at a high-performance point it raises VDD and applies forward bias to lower Vt for extra speed. DVFS alone moves only one of those two levers, so at low speed it still pays the full leakage of a fixed, fast Vt.

Technical Explanation

• Two knobs: VDD mainly sets dynamic power (C·V²·f); Vt mainly sets subthreshold leakage, which falls roughly exponentially as Vt rises.
• Body bias: reverse bias on the wells raises Vt and cuts leakage; forward bias lowers Vt and buys speed, but raises leakage and needs care around latch-up.
• Operating points: firmware picks from a table of (VDD, bias, f) triples instead of the (VDD, f) pairs used by plain DVFS, and moves between neighbouring rows.
• Ordering: going up, raise VDD and switch to forward bias before raising f; going down, lower f first, then drop VDD and apply reverse bias.
• Hardware cost: separate well bias supplies, on-chip bias generators, well taps tied to bias nets instead of VDD and VSS, and cells with bias pins.
• Limits: body effect weakens in advanced bulk and FinFET nodes, and strong reverse bias raises junction leakage, so the gain has a ceiling.
• Signoff cost: every (VDD, bias) pair is its own timing and leakage corner, so the libraries must be characterised at each bias point you ship.

Follow-up Question & Model Response

"Why not just use DVFS and power gating instead?"

Candidate Model Response: Power gating removes leakage only when the block is fully idle and costs wake-up time and state saving. DVFS cuts dynamic power but leaves leakage at whatever Vt the process gives you. DVTS covers the middle ground: the block stays alive at low speed while reverse bias trims its leakage. Whether that is worth the bias supplies depends on the node, since weak body effect shrinks the payoff. On an FD-SOI process with a strong back gate, the same bias range moves Vt far more, which is why DVTS shows up there most often.