How does a power switch's control and acknowledgment signal pair work?

Short Answer

The controller drives the switch control input, and the switch chain returns an acknowledge once its last cell has turned on. The ack tells the controller the virtual rail is really up, so restore and isolation release happen only after it arrives. In UPF you declare the pair with -control_port and -ack_port on create_power_switch (UPF).

Technical Explanation

• Control in: U_PC drives PSE into the first switch cell, and each cell passes the enable to the next through its buffered output.
• Ack out: the enable leaving the last cell becomes PSE_ACK, so it arrives only after every cell has turned on.
• Why wait: VDD1p0_SW ramps over the chain delay. Restoring or releasing isolation earlier reads a rail that is still rising.
• UPF model: -ack_port (UPF) names the ack net, and -ack_delay (UPF) sets how long after turn-on it changes in simulation.
• IEEE 1801-2015 makes an ack port an error unless the switch has a -supply_set (UPF) to power its control logic.
• Physical: connect_power_switch -mode daisy (ICC2) chains the placed cells from -source and wires the chain end to -ack_out.
• What breaks: a controller running on a fixed timer, not the ack, releases isolation into a half-powered domain at the slow corner.

# [UPF]  mychip.upf
create_power_switch COP_SW -domain PD_COP -supply_set SS_AON -input_supply_port {in VDD1p0} -output_supply_port {out VDD1p0_SW} -control_port {ctrl PSE} -ack_port {ack PSE_ACK} -ack_delay {ack 260ns} -on_state {ON in {ctrl}}
# [ICC2]  icc2_shell
connect_power_switch -source PSE -port_name pse_chain -mode daisy -ack_out PSE_ACK -ack_port_name pse_ack -voltage_area VA_COP
check_mv_design

What To Check

• The ack comes from the end of the chain, not from the first cell or the raw PSE net.
• U_PC waits for PSE_ACK before it restores and before it drops ISE.
• PSE and PSE_ACK are buffered with always-on cells where they cross the switched area.
• The ack polarity in UPF matches the library cell and the controller logic.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): In simulation PSE_ACK rises 260 ns after PSE, the modeled slow-corner chain delay, and SRE fires only after it.
• Suspicious (illustrative): PSE_ACK is taken from an early cell, so it rises while most of the chain is still off.
• Hard stop: U_PC drops ISE on a 200 ns timer while the slow-corner chain needs 260 ns.

What The Interviewer Is Testing

• Whether you know the ack closes the handshake and why the controller must wait for it.
• Whether you can tie the UPF ack model to the physical daisy chain.

Follow-up Question & Model Response

"Why not wait a fixed number of cycles instead of using an ack?"

Candidate Model Response: The chain delay changes with process, voltage, temperature and the number of switch cells. A timer sized for the typical corner is too short at the slow corner, and one sized for the worst case wastes wake-up time everywhere else. The ack measures the real chain on this die at this moment. Many designs keep a timer only as a watchdog in case the ack never arrives.