What is a mother-daughter power switch configuration, and why would you stage the switch turn-on?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A mother-daughter configuration pairs a weak switch transistor with a strong one on the same rail. The weak one turns on first and charges the domain slowly, and the strong one turns on after to give full current with low resistance. Staging this way keeps the in-rush current peak small, so neighbours on the same supply do not see a voltage dip.
Technical Explanation
- A discharged domain is a large capacitor; closing a strong switch at once pulls a big in-rush current spike.
- The weak transistor has high on-resistance, so it limits the charging current while the rail ramps.
- Once the rail is close to full, the strong transistor turns on to give low resistance for normal operation.
define_power_switch_cell(UPF) describes such a cell with-stage_1_enableand-stage_2_enable; in this example the weak devices are on stage 1.- Names vary: libraries do not agree on which one is called mother, so go by strength and enable order.
- Both enables come from always-on logic, and each stage has its own output so cells can be chained.
- The price is a longer wake-up, because the rail charges slowly before the strong stage can close.
Common Mistake
The Trap: Seeing two switches and assuming they are there for redundancy.
- If both stages get the same enable, the strong device closes on an empty rail and the full rush current returns.
- The shared supply dips, and neighbouring domains that never powered down can fail timing or reset.
Follow-up Question & Model Response
"How would you describe a two-stage switch in UPF?"
Candidate Model Response: IEEE 1801 lets create_power_switch (UPF) take two control ports. One port gives a partial on state and the other a full on state, so verification knows the rail only reaches full strength after the second enable. The library side of the cell is described with define_power_switch_cell (UPF) and its stage 1 and stage 2 enable options. The tool then maps the abstract switch to that cell.
Practical Example
Design Scenario: (illustrative) PD_COP has 2,000 switch cells, each with a weak and a strong transistor. Stage 1 enables ripple through the chain first and charge VDD1p0_SW to near 1.0 V at a modest current. Only after the stage 1 acknowledge returns does U_PC start the stage 2 chain. The peak current is a fraction of what turning on all strong devices together would pull. Started together, the strong chain could dip VDD1p0 enough to upset PD_CPU, which stays on.
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