ExpertQuestion 17 of 50

What happens if a retention strategy is given the wrong retention supply, and what UPF mechanism helps prevent this?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

If -retention_supply (UPF) points at a switched supply such as VDD1p0_SW, the shadow latches die with the domain and every retained value is lost at shutdown. Nothing fails until wake-up, when restore loads garbage. UPF helps in two ways: in implementation a missing retention supply is an error, and in simulation the default RET_SUP_COR semantics corrupt the register whenever its retention supply is off, so the bug shows up as X.

Schematic: retention flop in hatched PD_COP with main latch on VDD1p0_SW and shadow latch wired (red) to VDD1p0_SW instead of the always-on VDD1p0 strap, SAVE and RESTORE pins shown; a corrected inset shows the shadow latch on VDD1p0 through SS_AON. — Technical Reference DiagramWhat happens if a retention strategy is given the wrong retention supply, and what UPF mechanism helps prevent this?

Technical Reference DiagramWhat happens if a retention strategy is given the wrong retention supply, and what UPF mechanism helps prevent this?

Technical Explanation

Rule: the retention supply must stay on in every state where the primary is off; in MYCHIP that is SS_AON on VDD1p0.
Wrong supply: with VDD1p0_SW as the retention supply, the shadow latch loses power with the logic, so the value it saved disappears.
Simulation: RET_SUP_COR, the 1801-2015 default for -parameters on set_retention (UPF), corrupts the register when its retention supply is corrupt.
Setting NO_RET_SUP_COR to hide the X removes exactly the symptom that exposes this bug.
Static: confirm the supply behind SS_AON with report_supply_sets (ICC2), then run check_lp -stage upf (VCLP) and read every retention tag.
Implementation: 1801-2015 makes a missing retention supply an error, so always write it explicitly.
Legacy form (still accepted by ICC2/PT): -retention_power_net VDD1p0 -retention_ground_net VSS (UPF) on set_retention (UPF).

# [UPF]  mychip.upf
set_retention RET_COP -domain PD_COP -retention_supply SS_AON -save_signal {save high} -restore_signal {restore high} -parameters {RET_SUP_COR}
# [ICC2]  icc2_shell
report_supply_sets
report_mv_cells -retention -verbose
# [VC LP]  vc_static_shell
check_lp -stage upf
report_violations -app LP

What To Check

-retention_supply (UPF) names SS_AON, whose power is VDD1p0.
In every power state with PD_COP off, SS_AON is on.
Every inserted retention cell has its backup pin on VDD1p0.
Simulation keeps RET_SUP_COR, so a dead retention supply shows as X.

Command Checks & Actions

UPF (design.upf)

set_retention RET_COP -domain PD_COP -retention_supply SS_AON -save_signal {save high} -restore_signal {restore high} -parameters {RET_SUP_COR}

Puts the shadow latches on the always-on set and keeps corruption semantics on

ICC2 (icc2_shell)report_supply_sets

Shows the nets behind SS_AON and SS_COP

ICC2 (icc2_shell)report_mv_cells -retention -verbose

Shows inserted retention cells and their supplies

VC LP (vc_static_shell)check_lp -stage upf

Static check of the retention strategy against the power intent

VC LP (vc_static_shell)report_violations -app LP

Lists the resulting low-power violations

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): report_mv_cells -retention (ICC2) shows all 2,400 retention cells with backup pins on VDD1p0.
Suspicious (illustrative): Retention cells map correctly, but SS_AON has been updated elsewhere to a net that turns off in one test mode.
Hard stop: RET_COP names SS_COP, whose power is VDD1p0_SW, so every retained value is lost at shutdown.

Common Mistake

The Trap: Writing -retention_supply PD_COP.primary (UPF) because the strategy belongs to PD_COP.

PD_COP.primary is VDD1p0_SW, the rail being switched off, so the shadow latch dies with the logic it was meant to save.

What The Interviewer Is Testing

Whether you know the retention supply must be on whenever the primary is off.
Whether you know how simulation semantics and static checks expose a wrong supply.

Follow-up Question & Model Response

"Why can a wrong retention supply pass RTL simulation?"

Candidate Model Response: If the testbench never actually powers PD_COP down, the retention path is never exercised. Some teams also set NO_RET_SUP_COR, which stops corruption when the retention supply goes off. Either way the saved values look fine. A power-aware test that saves, powers off, powers on and restores with the default RET_SUP_COR exposes it at once.

Practical Example

Design Scenario: (illustrative) RET_COP was written with -retention_supply SS_COP, whose power is VDD1p0_SW. In power-aware simulation save rises at 100 ns, PSE falls at 200 ns, and the retention registers go X as VDD1p0_SW decays. After restore at 1.5 µs they still hold X, and the first instruction after wake-up reads garbage. Changing the supply to SS_AON on VDD1p0 fixes it.

Low-Power & UPF Handbook