What is the difference between primary power and backup (retention) power?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Primary power runs the whole domain and is the supply that turns off when the domain shuts down. Backup, or retention, power is a separate always-on supply that keeps a small part of each retention flop alive, so the saved bit survives. In Liberty the two show up as different pin roles on the same cell: primary_power and backup_power.
Technical Explanation
- Primary power: the domain's main, switched supply; it feeds the functional logic of the flop and everything else in the domain.
- Backup power: an always-on supply that feeds only the retention element, a shadow or balloon latch, inside the flop.
- Before power-down, SAVE copies the flop value into the shadow latch; after power-up, RESTORE copies it back.
- Modern UPF names the backup with
set_retention -retention_supply(UPF); legacy form (still accepted by ICC2/PT) uses-retention_power_net/-retention_ground_net. - Backup power can run lower than primary to save more leakage, if the library characterises the retention latch there.
- If the retention supply is tied to the switched net, the shadow latch loses power too and the restore brings back garbage.
# [UPF] design.upf
set_retention RET_COP -domain PD_COP -retention_supply SS_AON -save_signal {U_PC/save high} -restore_signal {U_PC/restore high}Common Mistake
The Trap: Pointing the retention supply at the domain's own switched primary.
- Everything passes structural checks, but after wake-up the block restarts with corrupt state, a bug only power-aware simulation or a static checker catches.
- Check that
-retention_supply(UPF) names an always-on set such as SS_AON, never the domain's own primary.
Follow-up Question & Model Response
"Does the backup supply make the whole flop always-on?"
Candidate Model Response: No. Only the small retention latch draws backup power; the main master and slave latches, the clock pins and the combinational logic are on primary power and turn off. That is why retention saves power: you keep a few transistors per flop leaking instead of the whole domain. The backup pin is routed as a secondary PG connection to an always-on strap. That strap carries only the small retention current, but it carries it for the whole time the domain sleeps.
Practical Example
Design Scenario: (illustrative) PD_COP has 4,000 retention flops. Primary VDD1p0_SW at 1.0 V goes off in sleep; backup VDD1p0 stays on. SAVE fires 2 cycles before the switch opens, RESTORE 2 cycles after it closes and power is good. Retention leakage is about 0.3 mW, against 12 mW if PD_COP stayed fully on, so retention keeps under 3% of the leakage. Cell names like RET_DFF_X1 are illustrative.
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