What is a level shifter and why is it needed?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A level shifter is a cell that converts a signal from the voltage swing of one domain to the swing of another. It is needed because a logic 1 from a lower-voltage domain is not high enough to turn off the PMOS of a gate on a higher supply. Without it the receiver leaks crowbar current and may switch late or read the wrong value.
Technical Explanation
- A level shifter has two supplies: an input side at the driver voltage and an output side at the receiver voltage.
- A 0.7 V "1" into a 1.0 V gate leaves the PMOS with 0.3 V of gate-source voltage, near its threshold, so it never turns off cleanly.
- Both transistors conduct, so crowbar current flows and the output sits weak and slow.
- Going from high to low voltage usually works logically, and whether a shifter is needed depends on the library and threshold settings.
- The threshold is the smallest voltage gap that triggers insertion; the tool reads supply voltages from the power states.
- An enable level shifter adds isolation for crossings where the source can switch off.
- Cell names such as LS_LH_X1 on this page are illustrative.
Common Mistake
The Trap: Checking only the nominal voltages and deciding two domains are "close enough".
- If one domain can drop to a lower DVFS level, a crossing that was safe at 0.9 V to 1.0 V becomes 0.7 V to 1.0 V and leaks.
- Always judge the need against the lowest voltage each domain can reach, taken from the power states.
Follow-up Question & Model Response
"How does the tool know which crossings need a level shifter if you write no strategy at all?"
Candidate Model Response: Level shifter strategies are optional in the UPF. The tool compares the driver and receiver voltages from the power states and inserts shifters automatically where the gap needs one. A strategy lets you control the rule, the location and the threshold. You still rely on the power states being complete, or real gaps go unseen. After insertion, check_mv_design (ICC2) reports any crossing still missing a shifter.
Practical Example
Design Scenario: (illustrative) PD_GPU runs at 0.7 V in its low mode and drives done into PD_AON at 1.0 V. The 0.3 V gap means the receiving inverter's PMOS stays partly on. An LS_LH_X1 low-to-high shifter, powered by both rails, restores a full 1.0 V swing. In the reverse direction, AON to GPU, the 1.0 V signal already switches the 0.7 V gates, so the library threshold decides.
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