What is the difference between an AND-type and an OR-type isolation cell (clamp value)?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
An AND-type isolation cell clamps its output to 0, and an OR-type isolation cell clamps its output to 1. The AND gate clamps when its enable input goes low, and the OR gate clamps when its enable goes high. In UPF you choose between them with the clamp value of the isolation strategy, and the tool maps that to the right cell.
Technical Explanation
- AND-type: OUT = D AND ISO_N. Driving ISO_N low forces OUT to 0 whatever D does.
- OR-type: OUT = D OR ISO. Driving ISO high forces OUT to 1 whatever D does.
- So the AND clamp has an active-low enable and the OR clamp an active-high one at the gate pin.
- In UPF,
set_isolation -clamp_value(UPF) is usually 0, 1 or latch; 0 maps to an AND-style cell and 1 to an OR-style cell. - The enable polarity in the strategy is set by
set_isolation -isolation_sense(UPF), high or low. - A wrong polarity means the cell clamps during normal operation and passes X while the domain is off.
- Choosing 0 or 1 per signal type is covered on the clamp-values page; cell names here are illustrative.
Common Mistake
The Trap: Picking the clamp by gate habit instead of by what the receiver treats as inactive.
- An OR clamp on an active-high enable holds that enable on for the whole shutdown, the exact opposite of the intent.
- The bug stays hidden in normal simulation and shows up only when the domain really powers down.
Follow-up Question & Model Response
"Your library only has AND-type isolation cells, but a signal needs a clamp to 1. What can you do?"
Candidate Model Response: The cleanest answer is an OR-type clamp-1 cell added to the library. Building clamp 1 from an AND cell with inverters on its input and output works logically, but the output inverter must also run on the always-on supply and adds delay. Some teams instead change the RTL so that 0 becomes the safe value. Whichever you pick, rerun the multivoltage checks to confirm the value the receiver sees during shutdown.
Practical Example
Design Scenario: (illustrative) PD_COP drives two signals into PD_MYCHIP: req (active-high) and rst_n (active-low reset). req needs clamp 0, so it gets ISO_AND_X1 with ISO_N from U_PC. rst_n needs clamp 1 so the receiver is not held in reset, so it gets ISO_OR_X1 with ISO driven high by U_PC. Both cells run on VDD1p0 and share one controller output, one of them through an inverter.
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