What is the difference between a low-to-high and a high-to-low voltage crossing?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A low-to-high crossing goes from a lower-voltage domain into a higher one, and a high-to-low crossing goes the other way. Low-to-high needs a level shifter, because the weak input cannot turn off the receiver PMOS. High-to-low often works without one, so it depends on the library and the threshold you set.
Technical Explanation
- Direction comes from the signal path, not from which domain is "main": one boundary usually has both types.
- Low-to-high needs a shifter, or the receiver leaks crowbar current and switches slowly.
- High-to-low is logically safe in most cases; the library threshold or
-thresholddecides whether a cell goes in. set_level_shifter -rule(UPF) takes low_to_high, high_to_low or both, and-locationpicks where the cell goes; this page uses self and parent.- A
-ruleor-no_shiftthat blocks insertion turns the missing shifter into a warning, not an error, incheck_mv_design(ICC2). - Cell names LS_L2H and LS_H2L on this page are illustrative.
# [UPF] design.upf
set_level_shifter LS_H2L -domain PD_GPU -applies_to inputs -rule high_to_low -location self
set_level_shifter LS_L2H -domain PD_GPU -applies_to outputs -rule low_to_high -location parent
# [ICC2] icc2_shell
check_mv_design
analyze_mv_design -level_shifter -through u_gpu/doneWhat To Check
- Every PD_GPU output feeding 0.9 V logic has a low-to-high shifter.
- High-to-low inputs match your library threshold decision, with no surprise gaps.
- The voltages in the power states cover the lowest DVFS level, not only nominal.
- Shifter warnings in
check_mv_design(ICC2) are explained by a deliberate-ruleor-no_shift.
Command Checks & Actions
set_level_shifter LS_L2H -domain PD_GPU -applies_to outputs -rule low_to_high -location parentLow-to-high strategy on PD_GPU outputs, cells placed in the receiving parent
set_level_shifter LS_H2L -domain PD_GPU -applies_to inputs -rule high_to_low -location selfHigh-to-low strategy on PD_GPU inputs, cells placed inside PD_GPU
check_mv_designReports missing level shifters and isolation cells as errors, or as warnings where a strategy blocks insertion
analyze_mv_design -level_shifter -through u_gpu/doneExplains why a shifter was not inserted on one net: domains, supplies and voltages on both sides
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative):
check_mv_designshows no level shifter errors, and every 0.75 V to 0.9 V output has an LS_L2H. - Suspicious (illustrative): Warnings on 0.9 V to 0.75 V inputs that nobody has checked against the library threshold.
- Hard stop: Any 0.75 V to 0.9 V crossing left without a shifter, error or warning.
Common Mistake
The Trap: Writing one strategy for the boundary and assuming it covers both directions.
- A single
-rule low_to_highstrategy on inputs does nothing for the outputs, so the real low-to-high crossings get no shifter.
What The Interviewer Is Testing
- That you name the direction from the signal path and know low-to-high is the one that needs a cell.
- That you can say what decides the high-to-low case: library threshold and strategy.
- That you check insertion with a report instead of trusting the UPF.
Follow-up Question & Model Response
"Why would a team still add high-to-low shifters when the logic works without them?"
Candidate Model Response: Some libraries characterise cells only for inputs up to their own supply, so a higher input is outside the timing model. A shifter also gives a clean, characterised delay across the boundary. The library threshold and your -threshold setting make that call per crossing. Check the library notes before you drop them.
Practical Example
Design Scenario: (illustrative) PD_GPU runs at 0.75 V and sits beside PD_AON at 0.9 V. Output done goes 0.75 V to 0.9 V, so LS_L2H is placed in the parent on the 0.9 V side. Input cfg comes 0.9 V to 0.75 V, and the library threshold asks for LS_H2L inside PD_GPU. After insertion, check_mv_design shows no level shifter errors on either path.
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