What is a power switch and what does it do?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A power switch is a large transistor cell placed between a real supply rail and a domain, so the power controller can disconnect that domain. When it is off, the domain's rail collapses and both dynamic and leakage power in the domain drop to near zero. You pay for it with area, a small IR drop through the switch, and wake-up time.
Technical Explanation
- A power switch cell has an input supply pin, an output switched supply pin, a control input and often an acknowledge output.
- A header switch gates the power rail; a footer switch gates the ground rail.
- Hundreds or thousands of switch cells work in parallel, chained so they turn on in sequence.
- The switch has on-resistance, so the domain sees a slightly lower voltage than the real rail.
- The control and acknowledge nets must stay powered, so they run through always-on logic.
- In UPF,
create_power_switch(UPF) describes the switch andmap_power_switch(UPF) binds it to a library cell. Names such as HEADER_X4 are illustrative. - More switches mean lower IR drop but more area, more leakage through the switches, and a longer chain to turn on.
Common Mistake
The Trap: Calling it "just a big transistor" and forgetting the control side.
- If the switch enable is buffered by cells on the switched rail, the domain can never be turned back on.
- The acknowledge path has the same trap: if it dies, the controller waits forever for a rail that is already up.
Follow-up Question & Model Response
"Why not use one huge switch instead of thousands of small ones?"
Candidate Model Response: The current has to reach every row of the domain, so switches are spread across the area to keep IR drop low. One big device would force all that current through a few routes. Many small cells can also be turned on in stages, which limits in-rush current. They also fit the standard-cell rows and power grid. In ICC2, create_power_switch_array (ICC2) places the cells across the voltage area and connect_power_switch (ICC2) connects their control pins.
Practical Example
Design Scenario: (illustrative) PD_COP in MYCHIP gets its supply VDD1p0_SW through HEADER_X4 cells connected to VDD1p0. U_PC drives PSE (high = on), and an always-on inverter turns it into SLEEP on the PMOS gates, so PSE low means SLEEP high and the switches open. VDD1p0_SW then decays to 0 V and PD_COP leakage disappears. On wake-up, U_PC raises PSE and waits for PSE_ACK from the last switch in the chain. If the switches drop 20 mV at full load, PD_COP sees about 0.98 V. In the UPF all of these cells are one switch, PD_COP_SW, mapped to HEADER_X4.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising