What is a "virtual rail," and how is it different from the primary supply?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A virtual rail is the supply net on the output side of a power switch, and it only exists behind that switch. The real supply feeds the switch and is always driven, while the virtual rail goes to 0 V whenever the switch is off. For a switchable domain, the virtual rail is the domain's primary supply.
Technical Explanation
- The real rail (for example VDD1p0) comes from the package and is never gated on the die.
- A virtual rail (VDD1p0_SW) is the switched output of the power switches.
- The logic in the domain connects only to the virtual rail, so it loses power when the switches open.
- The virtual rail sits a little below the real one, by the IR drop across the switch on-resistance.
- Isolation, retention and always-on cells must use the real rail, not the virtual one, or they die with the domain.
- In UPF the virtual rail is the output supply port of
create_power_switch(UPF), connected to a net such as VDD1p0_SW. - Domain primary:
create_power_domain PD_COP -supply {primary SS_COP}(UPF). Legacy form (still accepted by ICC2/PT):set_domain_supply_net(UPF).
Common Mistake
The Trap: Treating VDD1p0 and VDD1p0_SW as the same net because both are "the 1.0 V supply".
- A retention or always-on cell connected to the virtual rail loses power with the domain and fails silently in silicon.
check_mv_design(ICC2) and VC LP catch many of these, but only if the UPF names the right supply for each strategy.
Follow-up Question & Model Response
"What happens to the virtual rail when the switches turn off?"
Candidate Model Response: It stops being driven and decays toward 0 V as the domain's leakage drains the charge. It does not drop instantly, so the domain spends time at intermediate voltages. That is why isolation must already be on before the switches open. No always-on logic may depend on it. The expert page on virtual rails covers the decay in detail.
Practical Example
Design Scenario: (illustrative) In MYCHIP, VDD1p0 comes in at 1.0 V and feeds a column of header cells. Their outputs form VDD1p0_SW, which is the primary supply of PD_COP. At full load the switches drop 20 mV, so PD_COP runs at about 0.98 V. The retention latches and isolation cells in PD_COP take their power from VDD1p0. When the switches open, VDD1p0_SW falls toward 0 V while VDD1p0 stays at 1.0 V. In the UPF, supply set SS_COP uses VDD1p0_SW as its power function, and PD_COP names SS_COP as primary.
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