What is a "valid" vs an "invalid" signal, and why does this matter when a domain shuts down?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A valid signal sits at a clean logic 0 or logic 1, driven by a powered gate. When a domain shuts down, its outputs are no longer driven, so they float or settle somewhere between the rails. That invalid value can waste power in the receiving gate and make always-on logic act on garbage.
Technical Explanation
- A valid signal is actively driven to the receiver's 0 or 1 level.
- When the rail of the driving domain collapses, its outputs become invalid: floating, drifting, or stuck near mid-rail.
- A mid-rail input turns on both the PMOS and NMOS of the receiving gate, so crowbar current flows from VDD to VSS.
- The receiver can also read the value as either 0 or 1, and may trigger requests, interrupts or resets.
- Simulation shows the off-domain outputs as X, which is how verification catches the problem.
- The cure is an isolation cell that replaces the invalid value with a known one while the driver is off.
- Isolation must be on before the rail starts to drop, because the output turns invalid as soon as the supply sags.
Common Mistake
The Trap: Assuming an unpowered output simply reads as 0.
- Designers then skip isolation on signals that are "0 when idle", and the always-on side sees random values and leaks crowbar current.
- Plain RTL simulation does not model supplies, so the bug stays hidden until power-aware simulation or silicon.
Follow-up Question & Model Response
"Does a signal going from an always-on domain into a switched-off domain need isolation?"
Candidate Model Response: Usually not for validity, because the driver is still powered and driving a clean level. The receiver is unpowered, so there is no crowbar path in live logic. The concern is the other direction, where an unpowered driver feeds a live receiver. Some flows still isolate inputs of a shutdown domain to stop current flowing into unpowered gates. Check what your strategy and library expect.
Practical Example
Design Scenario: (illustrative) PD_COP drives req into the always-on PD_MYCHIP. With VDD1p0_SW at 1.0 V, req is a clean 1. After the switch opens, VDD1p0_SW decays and req drifts to about 0.5 V. The PD_MYCHIP receiver runs on VDD1p0, so both its transistors conduct and it leaks while reading an unknown value. An AND-type isolation cell on req holds it at 0 for the whole off period. In power-aware simulation, req without that cell shows X from the moment VDD1p0_SW goes off, which is how the gap is caught before tapeout.
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