What does "power-up" and "power-down" mean for a domain?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Power-down means the power controller opens the switch in front of a domain so its rail decays to 0 V and the logic inside stops leaking. Power-up means closing the switch again, letting the rail ramp back to full voltage, and bringing the logic back to a known state before it is used. Both are ordered sequences run by always-on logic, not a single flip of a switch.
Technical Explanation
- Power-down order: stop the clocks, assert isolation, save retention state, then turn the power switch off.
- Power-up order: turn the switch on, wait for the rail to settle, restore state, release isolation, then restart clocks.
- The power controller sits in an always-on domain, because it has to wake the very domain it shut down.
- Turning every switch on at once pulls a large in-rush current that can sag the supply of neighbours that are still running.
- Real designs stage the switches through a daisy chain, so wake-up takes time you must budget for.
- Get the order wrong and the always-on side reads X values, or retention flops save garbage.
- The acknowledge from the last switch in the chain tells the controller the rail is back, so firmware waits on it, not on a fixed delay.
Common Mistake
The Trap: Treating wake-up as instant: firmware starts using the domain the moment the switch enable goes high.
- The rail is still ramping, so the first transactions read X values or corrupt restored state.
- The fix is to wait for the switch acknowledge, then restore, then release isolation.
Follow-up Question & Model Response
"Why does the sequence release isolation last on power-up?"
Candidate Model Response: While the rail ramps, the outputs of the waking domain are still invalid. If isolation dropped first, the always-on receivers would see those X values and could act on them. Restoring retention state first also puts the outputs back to their pre-sleep values. Only then is it safe to let the real signals through. Power-down runs the same logic in reverse, so isolation goes on before anything in the domain changes.
Practical Example
Design Scenario: (illustrative) PD_COP in MYCHIP runs on VDD1p0_SW, switched from VDD1p0. Power controller U_PC stops the PD_COP clock, asserts ISE (isolation), pulses save, then drops PSE to open the switch. On wake it raises PSE and waits for PSE_ACK, which returns only after the switch daisy chain has turned on. Assume 2,000 switch cells at 30 ps each: about 60 ns before the chain completes. U_PC then pulses restore and releases ISE. Only after that does it restart the PD_COP clock, so the first transaction sees a settled 1.0 V rail and valid outputs.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising