What is a switched ground net, and how does it relate to a footer switch?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A switched ground net is the ground rail of a domain that reaches real ground only through a footer switch. The footer is an NMOS transistor between that net, often called VVSS, and the real VSS. When the footer opens, VVSS is cut off from VSS and drifts up toward VDD, so the domain stops conducting.
Technical Explanation
- A footer switch is an NMOS cell that connects the domain's ground pins to the real ground rail.
- The net between the cells and the footer is the switched ground, or VVSS.
- When the footer is on, VVSS sits slightly above VSS because of the switch on-resistance.
- When it is off, VVSS floats up toward VDD and the logic has no current path.
- VDD still reaches every cell, so the domain's outputs are invalid but not at 0 V; isolation is still needed.
- Always-on, isolation and retention cells must return to the real VSS, not VVSS.
- NMOS carries more current per width than PMOS, so a footer can be smaller than a header for the same drop.
Common Mistake
The Trap: Assuming only VDD can be gated, and wiring every special cell to the domain ground out of habit.
- Footer designs then get isolation and always-on cells tied to VVSS, and those cells stop working when the footer opens.
- The fix is to tie them to the real VSS and rerun the multivoltage checks on the ground connections.
Follow-up Question & Model Response
"Why might ground bounce be a concern with footer switching?"
Candidate Model Response: All the domain's return current flows through the footers, so VVSS rises above VSS by the IR drop across them. That raises the local ground seen by the logic and reduces noise margin. During wake-up, the rush of current can also disturb the shared VSS. Header designs are more common in standard-cell flows. The expert page on header versus footer covers the trade-off.
Practical Example
Design Scenario: (illustrative) A 0.9 V DSP block uses FOOTER_X4 cells between VVSS and VSS, with VDD at 0.9 V going straight to the rows. With the footers on and 20 mV of drop, VVSS sits at about 20 mV. When SLEEP_N goes low, the footers open and VVSS drifts toward 0.9 V. Isolation cells on the block's outputs run between VDD and the real VSS. A retention flop in the block keeps its shadow latch between VDD and the real VSS, so the saved state survives while VVSS floats.
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