What is multivoltage design?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Multivoltage design runs different blocks of one die at different supply voltages. Blocks that need speed get a higher voltage, and everything else runs lower to save power, since dynamic power scales with the square of the voltage.
Technical Explanation
- Each block at its own voltage is a voltage island. In UPF it is a power domain; in the floorplan it is placed in a voltage area.
- Lower voltage cuts dynamic power sharply but slows gates, so you lower it only where timing allows.
- Every signal between islands at different voltages is a voltage crossing that may need a level shifter.
- Except for level shifters, all cells in one voltage area run at the same voltage.
- Timing needs libraries characterized at every voltage in use, and every supply net needs a voltage, from the power states or
set_voltage(ICC2). - Normally one voltage area holds one power domain, but domains with equivalent primary supplies can share one area through
shared_voltage_area(UPF). - Miss a level shifter on a low-to-high crossing and the receiving gate never switches off cleanly, burning current or failing outright.
Formula Or Decision Rule
- Dynamic power: P = Ī± Ā· C Ā· VĀ² Ā· f
- Voltage saving (illustrative): 0.9 V instead of 1.0 V gives (0.9/1.0)Ā² = 0.81, about 19% less dynamic power at the same frequency.
Common Mistake
The Trap: Treating multivoltage (fixed voltages per block) and DVFS (one block changing voltage over time) as the same thing.
- DVFS adds timing at every operating point and a safe sequencing rule that a fixed-voltage island does not need.
- Mixing them up also hides the real cost of fixed islands: a level shifter on every low-to-high crossing and a voltage area per island in the floorplan.
Follow-up Question & Model Response
"Can two different power domains share one voltage area?"
Candidate Model Response: Yes, when their primary supplies are equivalent: connected in the UPF, physically connected, or equivalent in the power state table. You list the domains in the shared_voltage_area attribute with set_design_attributes (UPF), or add a domain with set_voltage_area -add_power_domains (ICC2). One domain in the set acts as the primary domain. The rows in that area still carry a single primary supply.
Practical Example
Design Scenario: (illustrative) A sensor hub runs PD_MYCHIP at 1.0 V for its bus, PD_CPU at 0.9 V and PD_SNS at 0.75 V. The sensor filter meets timing at 0.75 V with margin, so it saves about 44% dynamic power versus 1.0 V ((0.75)Ā² ā 0.56). Every PD_SNS output that feeds the 1.0 V bus crosses low to high and gets a level shifter. PD_CPU outputs into PD_SNS go high to low, so whether they need one depends on the library and the -threshold of set_level_shifter (UPF).
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