What is the difference between a switched power supply and an always-on power supply?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A switched supply sits behind a power switch and disappears when the switch opens; it is often called the virtual rail. An always-on supply comes straight from the regulator and never turns off during operation. The switch, its control path, isolation cells and retention latches must run on the always-on supply, because they have to work while the switched rail is off.
Technical Explanation
- Always-on supply: the real rail from the package, such as VDD1p0; it powers the switch input and anything that must survive shutdown.
- Switched supply: the output of the switch, such as VDD1p0_SW; the domain's ordinary cells sit on it.
- In UPF,
create_power_switch(UPF) links them: always-on on the input supply port, switched net on the output. - A header switch is a PMOS between VDD and the virtual VDD; a footer is an NMOS between the virtual VSS and VSS.
- Needs always-on power: switch enable buffers, isolation cells, the power controller, retention latches and feedthrough buffers.
- Put a switch-enable buffer on the switched rail and the domain cannot be turned back on.
# [UPF] design.upf
create_power_switch SW_COP -domain PD_COP -input_supply_port {vin VDD1p0} -output_supply_port {vout VDD1p0_SW} -control_port {sw_en U_PC/PSE} -on_state {ON vin {sw_en}}Common Mistake
The Trap: Assuming every cell placed inside a switchable domain loses power at shutdown.
- Always-on cells can sit inside that region on the switched row rail but take their real supply from an always-on strap through a secondary PG pin; forget them and control or feedthrough paths die.
- List every cell that must work during shutdown and confirm its real supply is VDD1p0, not the row rail.
Follow-up Question & Model Response
"Why not make the whole chip always-on and skip the complexity?"
Candidate Model Response: Because an idle but powered block keeps leaking, and at advanced nodes that leakage is a large share of standby power. Switching it off cuts that leakage to the small amount that flows through the open switches. The price is the switch area, a slight IR drop through the switch when on, wake-up time and the isolation and retention cells. For blocks idle most of the time, the trade is worth it.
Practical Example
Design Scenario: (illustrative) MYCHIP PD_COP: VDD1p0 at 1.0 V feeds 300 header switch cells (HEADER_X4, an illustrative name) whose outputs form VDD1p0_SW. In sleep, U_PC drops the switch enable and VDD1p0_SW decays to near 0 V. The isolation cells on PD_COP outputs, the enable buffer chain and 4,000 retention latches stay on VDD1p0 the whole time. Check: the switch enable PSE comes from U_PC in PD_MYCHIP, so it is valid while VDD1p0_SW is off.
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