BeginnerQuestion 46 of 50

What is the stack effect (transistor stacking), and how does it reduce subthreshold leakage in an idle logic gate?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

The stack effect is the drop in subthreshold leakage when two or more off transistors sit in series. The node between them rises to a small positive voltage, which pushes the upper transistor harder off and cuts the voltage across the lower one, so the stack leaks much less than a single off transistor.

Schematic comparing one off NMOS leaking I0 with two stacked off NMOS whose middle node Vx settles to a small positive voltage, marking negative Vgs and body effect on the top device and reduced Vds on the bottom device. — Technical Reference DiagramWhat is the stack effect (transistor stacking), and how does it reduce subthreshold leakage in an idle logic gate?

Technical Reference DiagramWhat is the stack effect (transistor stacking), and how does it reduce subthreshold leakage in an idle logic gate?

Technical Explanation

Take two off NMOS in series. Leakage through both charges the middle node to a small Vx above ground.
The upper transistor now has its source at Vx and gate at 0 V, so Vgs is negative, which cuts its leakage sharply.
Its source is also above the body, so the body effect raises its threshold voltage.
The lower transistor sees only Vx across it, so DIBL is small and its leakage falls too.
The reduction is process dependent, often several times less than one off device (illustrative).
The saving depends on the inputs: a NAND with one input high has only one off pull-down device, so it leaks like a single transistor.
Tools exploit it with input vector control: park idle gates in the input state that turns off the most stacked devices.

Common Mistake

The Trap: Assuming two off transistors in series leak as much as, or more than, one.

Hand estimates then overstate idle leakage, and you miss a free saving from restructuring or idle input vectors.
The opposite trap is stacking devices everywhere: a series stack has less drive current, so it only suits paths with timing slack.

Follow-up Question & Model Response

"How do power-gating footers relate to the stack effect?"

Candidate Model Response: A footer switch in series with the logic pull-down adds one more off device to every leakage path when the block sleeps. The virtual ground node rises, which gives the same negative Vgs and body-effect benefit to the logic above. A high-Vt footer pushes this further. That is part of why power gating cuts leakage by a large factor.

Practical Example

Design Scenario: (illustrative) A 2-input NAND sits idle with both inputs at 0. Both pull-down NMOS are off in series, and Vx settles near 80 mV. Leakage through the stack comes out several times lower than an inverter NMOS of the same width. Parking idle NAND inputs at 00 instead of 01 or 10 keeps that saving. In the 01 or 10 state only one pull-down NMOS is off, it sees the full supply across it, and the gate leaks about like the inverter.

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