What is the trade-off between high-threshold-voltage (HVt) and low-threshold-voltage (LVt) cells?

Short Answer

LVT cells switch faster because they turn on at a lower gate voltage, but they leak much more when off. HVT cells leak far less but are slower. You use HVT everywhere timing allows and spend LVT only on paths that cannot meet timing otherwise.

Technical Explanation

• Threshold voltage (Vt): lowering Vt raises drive current, so the gate is faster, but subthreshold leakage rises exponentially.
• Illustratively, one Vt step can change leakage by around 10x while delay changes by only 10-30%, depending on the library.
• Libraries usually offer HVT, SVT and LVT (sometimes ULVT) with the same footprint, so the tool can swap them in place.
• The flow starts mostly HVT or SVT and swaps to lower-Vt cells only on critical paths; leakage recovery swaps non-critical cells back to higher Vt.
• Too much LVT and leakage blows the budget at hot corners; too little and setup fails at the slow corner.
• LVT also shifts more with process variation, so heavy LVT use widens the spread between chips.
• Read the Vt mix in every run's report; a jump in LVT share is the early warning before leakage signoff fails.

Follow-up Question & Model Response

"Where would you still choose LVT?"

Candidate Model Response: On the few paths that are truly timing critical: the CPU core's tightest pipeline stages, clock-to-output paths into hard macros and some clock-tree buffers. Those blocks are usually active when they run, so dynamic power dominates and the extra leakage costs relatively little. Idle-heavy logic such as always-on control should stay HVT. A good mix is often mostly HVT with a small single-digit percentage of LVT, depending on the design. Re-check leakage at the fast-hot corner after every round of LVT swaps, because that is where the extra LVT shows up first.