What causes leakage power in a CMOS transistor?

Short Answer

An off transistor still conducts a small current through three main paths: subthreshold conduction under the channel, tunnelling through the gate oxide, and reverse-biased junction leakage including GIDL. At advanced nodes subthreshold leakage dominates, because threshold voltages were lowered to keep gates fast. Gate leakage was brought down by high-k metal gates, so it matters less than it once did.

Technical Explanation

• Subthreshold leakage: with gate voltage below Vt, carriers still diffuse from source to drain; current rises exponentially as Vt drops.
• Gate leakage: thin oxide lets electrons tunnel through the gate; high-k dielectrics thickened the physical layer and cut this path.
• Junction leakage: reverse-biased drain and source diodes leak into the well, rising with temperature.
• GIDL (gate-induced drain leakage): a strong field where gate overlaps drain pulls current into the substrate, worse at high drain bias.
• Subthreshold leakage grows steeply with temperature and at the fast corner, so it sets the leakage signoff number.
• Leakage also depends on input state: which transistors in a stack are off changes the cell's leakage, so libraries list it per input pattern.
• These mechanisms drive the fixes: higher-Vt cells, transistor stacking, reverse body bias and power gating.

Follow-up Question & Model Response

"Why does a stack of two off transistors leak less than one?"

Candidate Model Response: The node between the two transistors floats up to a small positive voltage. That gives the upper transistor a negative gate-to-source voltage and raises its effective Vt through the body effect. The lower transistor now sees only that small node voltage across it, so drain-induced barrier lowering drops too, and the combined subthreshold current falls sharply. Designers use this stack effect in sleep vectors and in stacked-transistor leakage cells.