Why is low-power design necessary in modern chip design?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Power now limits what a chip can do as much as timing and area do. Battery life, heat the package can remove, and leakage that grows at every smaller node all cap performance, so power has to be planned from RTL onward. Each of those limits shows up as a concrete physical-design task: domains, switches, multi-Vt mixes and a stronger power grid.
Technical Explanation
- Battery life: a phone or wearable spends most of its time idle, so standby leakage decides how many hours the battery lasts.
- Thermal limit: the package and heatsink can only remove so many watts; past that the chip throttles its clock or overheats.
- Leakage growth: lower threshold voltages at small nodes make transistors leak more when off, so idle blocks burn real power.
- Current delivery: more watts at lower voltage means more amps, which raises IR drop and electromigration risk in the power grid.
- The PD consequence: switchable power domains with isolation and retention, multi-Vt cell mixes, clock gating and a denser power mesh.
- Ignore power until signoff and you find thermal or IR failures when the floorplan is frozen, which is the most expensive time to fix them.
Common Mistake
The Trap: Treating power as a battery problem only, and checking it once at the end of the flow.
- Plugged-in server and automotive chips hit thermal and IR-drop limits too, and those need domains and grid planning early.
- Late discovery forces a re-floorplan or a slower clock, both far costlier than planning power from RTL.
Follow-up Question & Model Response
"If a chip is always plugged in, why would it still need power gating?"
Candidate Model Response: Because the limit is heat and current, not the battery. A server SoC with idle cores still pays leakage on every one of them, and that leakage adds to the heat the package must remove. Gating idle cores frees thermal headroom that active cores can spend on a higher clock. It also cuts the average current the grid must deliver.
Practical Example
Design Scenario: (illustrative) A mobile SoC has a 3 W thermal budget. With the GPU idle but powered, leakage costs 0.4 W, leaving 2.6 W for the CPU cluster. Putting the GPU in a switchable domain PD_GPU drops that to near zero, so the CPU can run a higher clock inside the same 3 W. Check the gain: 0.4 W is about 13% of the 3 W budget, and moving the CPU from 2.6 W to 3.0 W is up to about 15% more clock at fixed voltage, if its power is mostly dynamic. The cost: a power-switch array, isolation cells on PD_GPU outputs and an always-on controller.
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